Hi Stefan, On Fri, 24 Jul 2020 at 04:09, Stefan Roese <s...@denx.de> wrote: > > From: Suneel Garapati <sgarap...@marvell.com> > > Enable PCI memory regions in ranges property to be of multiple entry. > This helps to add support for SoC's like OcteonTX/TX2 where every > peripheral is on PCI bus. > > Signed-off-by: Suneel Garapati <sgarap...@marvell.com> > Cc: Simon Glass <s...@chromium.org> > Cc: Bin Meng <bmeng...@gmail.com> > > Signed-off-by: Stefan Roese <s...@denx.de> > --- > > Changes in v1: > - Change patch subject > - Enhance Kconfig help descrition > - Use if() instead of #if > > drivers/pci/Kconfig | 10 ++++++++++ > drivers/pci/pci-uclass.c | 9 ++++++--- > 2 files changed, 16 insertions(+), 3 deletions(-)
This needs an update to a sandbox test to handle this behaviour.
