On Tue, Jul 28, 2020 at 12:58:30PM -0600, Simon Glass wrote: > Hi Marty, > > On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanet...@startmail.com> wrote: > > > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > > Hi Marty, > > > > > > Did you check spl_boot_device()? > > > > > After sending the initial email I noticed your binman work, which does > > some of the stuff I think I need. My current setup is as follows: > > > > > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > > speciy BOB but not KEVIN. > > Yeah. I worked that in. > > > > Currently, a rom which is built with these changes (assuming u-boot.rom > > is what I want for SPI booting; strange its only 4mb, aren't these > > devices 8mb flash?) I get no output at all over the servo, aside from > > the EC. > > I think it is only 4MB. > Nah, kevin is deffo 8mb flash chip. Otherwise I wouldn't have been able to shove a 7.xmb kernel+initramfs into a coreboot image and flash it.
I have to pad the u-boot.rom with dd to flash it. > I am not sure that I have a kevin. Did you try using the debug UART? > Yeah, assuming you mean `dut-control cpu_uart_pty` with a servo hooked up, and using `socat READLINE /dev/pts/something`. I get no output, but the same chromiumos chroot with vanilla coreboot+depthcharge and hardware config does do output as expected. Perhaps I'm missing something simple. > Regards, > Simon