On Tue, Aug 11, 2020 at 04:01:10PM +0800, Chee Hong Ang wrote:

> Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> for booting up Cyclone5/Arria10.
> 
> For Cyclone5 using NAND flash image layout for 128 KB memory blocks,
> 'make u-boot-with-nand-spl.sfp' to generate spl/u-boot-nand-splx4.sfp
> which contains four 128KB SPL images (each 64KB SPL is followed by
> 64KB of zero-padding).
> 
> Signed-off-by: Chee Hong Ang <chee.hong....@intel.com>
> ---
>  Makefile | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 4483a9b..f4631f1 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1582,8 +1582,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
>  ifneq ($(CONFIG_ARCH_SOCFPGA),)
>  quiet_cmd_socboot = SOCBOOT $@
>  cmd_socboot = cat    spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
> -                     spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
> -                     u-boot.img > $@ || rm -f $@
> +                     spl/u-boot-spl.sfp \
> +                     spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> +           cat       spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
>  u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
>       $(call if_changed,socboot)
>  
> @@ -1592,8 +1593,10 @@ cmd_socnandboot =  dd if=/dev/zero 
> of=spl/u-boot-spl.pad bs=64 count=1024 ; \
>                  cat  spl/u-boot-spl.sfp spl/u-boot-spl.pad \
>                       spl/u-boot-spl.sfp spl/u-boot-spl.pad \
>                       spl/u-boot-spl.sfp spl/u-boot-spl.pad \
> -                     spl/u-boot-spl.sfp spl/u-boot-spl.pad \
> -                     u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad
> +                     spl/u-boot-spl.sfp \
> +                     spl/u-boot-spl.pad > spl/u-boot-nand-splx4.sfp ; \
> +                cat  spl/u-boot-nand-splx4.sfp u-boot.img > $@ || \
> +                rm   -f $@ spl/u-boot-spl.pad
>  u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
>       $(call if_changed,socnandboot)

It's not immediately clear to me why we're doing this here, rather than
instructing the user to write the file 4 times when programming.  On TI
platforms, even on NAND, for forever there's been multiple locations the
ROM will check for the loader.  Is there a reason to not handle this at
that level?

-- 
Tom

Attachment: signature.asc
Description: PGP signature

Reply via email to