Hi Christophe
On 7/31/20 9:53 AM, Christophe Kerello wrote:
> This patch removes custom macros and uses FIELD_PREP and FIELD_GET macros.
>
> Signed-off-by: Christophe Kerello <christophe.kere...@st.com>
> ---
>
> drivers/mtd/nand/raw/stm32_fmc2_nand.c | 120
> +++++++++++++++------------------
> 1 file changed, 56 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> index 9718bae..eba1ded 100644
> --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
> @@ -10,6 +10,7 @@
> #include <log.h>
> #include <nand.h>
> #include <reset.h>
> +#include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/delay.h>
> #include <linux/err.h>
> @@ -60,20 +61,16 @@
> /* Register: FMC2_PCR */
> #define FMC2_PCR_PWAITEN BIT(1)
> #define FMC2_PCR_PBKEN BIT(2)
> -#define FMC2_PCR_PWID_MASK GENMASK(5, 4)
> -#define FMC2_PCR_PWID(x) (((x) & 0x3) << 4)
> +#define FMC2_PCR_PWID GENMASK(5, 4)
> #define FMC2_PCR_PWID_BUSWIDTH_8 0
> #define FMC2_PCR_PWID_BUSWIDTH_16 1
> #define FMC2_PCR_ECCEN BIT(6)
> #define FMC2_PCR_ECCALG BIT(8)
> -#define FMC2_PCR_TCLR_MASK GENMASK(12, 9)
> -#define FMC2_PCR_TCLR(x) (((x) & 0xf) << 9)
> +#define FMC2_PCR_TCLR GENMASK(12, 9)
> #define FMC2_PCR_TCLR_DEFAULT 0xf
> -#define FMC2_PCR_TAR_MASK GENMASK(16, 13)
> -#define FMC2_PCR_TAR(x) (((x) & 0xf) << 13)
> +#define FMC2_PCR_TAR GENMASK(16, 13)
> #define FMC2_PCR_TAR_DEFAULT 0xf
> -#define FMC2_PCR_ECCSS_MASK GENMASK(19, 17)
> -#define FMC2_PCR_ECCSS(x) (((x) & 0x7) << 17)
> +#define FMC2_PCR_ECCSS GENMASK(19, 17)
> #define FMC2_PCR_ECCSS_512 1
> #define FMC2_PCR_ECCSS_2048 3
> #define FMC2_PCR_BCHECC BIT(24)
> @@ -83,17 +80,17 @@
> #define FMC2_SR_NWRF BIT(6)
>
> /* Register: FMC2_PMEM */
> -#define FMC2_PMEM_MEMSET(x) (((x) & 0xff) << 0)
> -#define FMC2_PMEM_MEMWAIT(x) (((x) & 0xff) << 8)
> -#define FMC2_PMEM_MEMHOLD(x) (((x) & 0xff) << 16)
> -#define FMC2_PMEM_MEMHIZ(x) (((x) & 0xff) << 24)
> +#define FMC2_PMEM_MEMSET GENMASK(7, 0)
> +#define FMC2_PMEM_MEMWAIT GENMASK(15, 8)
> +#define FMC2_PMEM_MEMHOLD GENMASK(23, 16)
> +#define FMC2_PMEM_MEMHIZ GENMASK(31, 24)
> #define FMC2_PMEM_DEFAULT 0x0a0a0a0a
>
> /* Register: FMC2_PATT */
> -#define FMC2_PATT_ATTSET(x) (((x) & 0xff) << 0)
> -#define FMC2_PATT_ATTWAIT(x) (((x) & 0xff) << 8)
> -#define FMC2_PATT_ATTHOLD(x) (((x) & 0xff) << 16)
> -#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
> +#define FMC2_PATT_ATTSET GENMASK(7, 0)
> +#define FMC2_PATT_ATTWAIT GENMASK(15, 8)
> +#define FMC2_PATT_ATTHOLD GENMASK(23, 16)
> +#define FMC2_PATT_ATTHIZ GENMASK(31, 24)
> #define FMC2_PATT_DEFAULT 0x0a0a0a0a
>
> /* Register: FMC2_BCHISR */
> @@ -106,28 +103,23 @@
> /* Register: FMC2_BCHDSR0 */
> #define FMC2_BCHDSR0_DUE BIT(0)
> #define FMC2_BCHDSR0_DEF BIT(1)
> -#define FMC2_BCHDSR0_DEN_MASK GENMASK(7, 4)
> -#define FMC2_BCHDSR0_DEN_SHIFT 4
> +#define FMC2_BCHDSR0_DEN GENMASK(7, 4)
>
> /* Register: FMC2_BCHDSR1 */
> -#define FMC2_BCHDSR1_EBP1_MASK GENMASK(12, 0)
> -#define FMC2_BCHDSR1_EBP2_MASK GENMASK(28, 16)
> -#define FMC2_BCHDSR1_EBP2_SHIFT 16
> +#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0)
> +#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16)
>
> /* Register: FMC2_BCHDSR2 */
> -#define FMC2_BCHDSR2_EBP3_MASK GENMASK(12, 0)
> -#define FMC2_BCHDSR2_EBP4_MASK GENMASK(28, 16)
> -#define FMC2_BCHDSR2_EBP4_SHIFT 16
> +#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0)
> +#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16)
>
> /* Register: FMC2_BCHDSR3 */
> -#define FMC2_BCHDSR3_EBP5_MASK GENMASK(12, 0)
> -#define FMC2_BCHDSR3_EBP6_MASK GENMASK(28, 16)
> -#define FMC2_BCHDSR3_EBP6_SHIFT 16
> +#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0)
> +#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16)
>
> /* Register: FMC2_BCHDSR4 */
> -#define FMC2_BCHDSR4_EBP7_MASK GENMASK(12, 0)
> -#define FMC2_BCHDSR4_EBP8_MASK GENMASK(28, 16)
> -#define FMC2_BCHDSR4_EBP8_SHIFT 16
> +#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
> +#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
>
> #define FMC2_NSEC_PER_SEC 1000000000L
>
> @@ -190,22 +182,22 @@ static void stm32_fmc2_nfc_timings_init(struct
> nand_chip *chip)
> u32 pmem, patt;
>
> /* Set tclr/tar timings */
> - pcr &= ~FMC2_PCR_TCLR_MASK;
> - pcr |= FMC2_PCR_TCLR(timings->tclr);
> - pcr &= ~FMC2_PCR_TAR_MASK;
> - pcr |= FMC2_PCR_TAR(timings->tar);
> + pcr &= ~FMC2_PCR_TCLR;
> + pcr |= FIELD_PREP(FMC2_PCR_TCLR, timings->tclr);
> + pcr &= ~FMC2_PCR_TAR;
> + pcr |= FIELD_PREP(FMC2_PCR_TAR, timings->tar);
>
> /* Set tset/twait/thold/thiz timings in common bank */
> - pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
> - pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
> - pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
> - pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
> + pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
> + pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
> + pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
> + pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
>
> /* Set tset/twait/thold/thiz timings in attribut bank */
> - patt = FMC2_PATT_ATTSET(timings->tset_att);
> - patt |= FMC2_PATT_ATTWAIT(timings->twait);
> - patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
> - patt |= FMC2_PATT_ATTHIZ(timings->thiz);
> + patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
> + patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
> + patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
> + patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
>
> writel(pcr, nfc->io_base + FMC2_PCR);
> writel(pmem, nfc->io_base + FMC2_PMEM);
> @@ -228,13 +220,13 @@ static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
> }
>
> /* Set buswidth */
> - pcr &= ~FMC2_PCR_PWID_MASK;
> + pcr &= ~FMC2_PCR_PWID;
> if (chip->options & NAND_BUSWIDTH_16)
> - pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
> + pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
>
> /* Set ECC sector size */
> - pcr &= ~FMC2_PCR_ECCSS_MASK;
> - pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
> + pcr &= ~FMC2_PCR_ECCSS;
> + pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
>
> writel(pcr, nfc->io_base + FMC2_PCR);
> }
> @@ -264,9 +256,9 @@ static void stm32_fmc2_nfc_set_buswidth_16(struct
> stm32_fmc2_nfc *nfc,
> {
> u32 pcr = readl(nfc->io_base + FMC2_PCR);
>
> - pcr &= ~FMC2_PCR_PWID_MASK;
> + pcr &= ~FMC2_PCR_PWID;
> if (set)
> - pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
> + pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
> writel(pcr, nfc->io_base + FMC2_PCR);
> }
>
> @@ -497,16 +489,16 @@ static int stm32_fmc2_nfc_bch_correct(struct mtd_info
> *mtd, u8 *dat,
> if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
> return -EBADMSG;
>
> - pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
> - pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
> - pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
> - pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
> - pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
> - pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
> - pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
> - pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
> + pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
> + pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
> + pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
> + pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
> + pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
> + pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
> + pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
> + pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
>
> - den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
> + den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
> for (i = 0; i < den; i++) {
> if (pos[i] < eccsize * 8) {
> __change_bit(pos[i], (unsigned long *)dat);
> @@ -581,7 +573,7 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc
> *nfc)
> pcr |= FMC2_PCR_PBKEN;
>
> /* Set buswidth to 8 bits mode for identification */
> - pcr &= ~FMC2_PCR_PWID_MASK;
> + pcr &= ~FMC2_PCR_PWID;
>
> /* ECC logic is disabled */
> pcr &= ~FMC2_PCR_ECCEN;
> @@ -592,14 +584,14 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc
> *nfc)
> pcr &= ~FMC2_PCR_WEN;
>
> /* Set default ECC sector size */
> - pcr &= ~FMC2_PCR_ECCSS_MASK;
> - pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
> + pcr &= ~FMC2_PCR_ECCSS;
> + pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
>
> /* Set default tclr/tar timings */
> - pcr &= ~FMC2_PCR_TCLR_MASK;
> - pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
> - pcr &= ~FMC2_PCR_TAR_MASK;
> - pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
> + pcr &= ~FMC2_PCR_TCLR;
> + pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
> + pcr &= ~FMC2_PCR_TAR;
> + pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
>
> /* Enable FMC2 controller */
> bcr1 |= FMC2_BCR1_FMC2EN;
Reviewed-by: Patrice Chotard <patrice.chot...@st.com>
Thanks
Patrice
