From: Suneel Garapati <sgarap...@marvell.com>
For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.
Signed-off-by: Suneel Garapati <sgarap...@marvell.com>
Reviewed-by: Simon Glass <s...@chromium.org>
Signed-off-by: Stefan Roese <s...@denx.de>
---
Changes in v2:
- Add Reviewed-by tag from Simon
- Add note about adding a Kconfig option for AHCI quirks, once there
are multiple quirks
Changes in v1:
- Change patch subject
- Use constants from pci_ids.h instead of hardcoded values
drivers/ata/ahci.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 47cdea1f58..22bc0d3b10 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1198,10 +1198,25 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong
base)
int ahci_probe_scsi_pci(struct udevice *ahci_dev)
{
ulong base;
+ u16 vendor, device;
base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
+ /*
+ * Note:
+ * Right now, we have only one quirk here, which is not enough to
+ * introduce a new Kconfig option to select this. Once we have more
+ * quirks in this AHCI code, we should add a Kconfig option for
+ * this though.
+ */
+ dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
+ dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
+
+ if (vendor == PCI_VENDOR_ID_CAVIUM &&
+ device == PCI_DEVICE_ID_CAVIUM_SATA)
+ base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
+ PCI_REGION_MEM);
return ahci_probe_scsi(ahci_dev, base);
}
#endif
--
2.28.0
