Since we have a driver for the reset controller, lets add the necessary node.
Signed-off-by: Robert Marko <robert.ma...@sartura.hr>
---
arch/arm/Kconfig | 1 +
arch/arm/dts/qcom-ipq4019.dtsi | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 52c45292e9..a636049687 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -767,6 +767,7 @@ config ARCH_IPQ40XX
select DM
select DM_GPIO
select DM_SERIAL
+ select DM_RESET
select MSM_SMEM
select PINCTRL
select CLK
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 9d21b15bb3..67122de9c0 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -10,6 +10,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/reset/qcom,ipq40xx-reset.h>
/ {
#address-cells = <1>;
@@ -57,6 +58,14 @@
u-boot,dm-pre-reloc;
};
+ reset: gcc-reset@1800000 {
+ compatible = "qcom,gcc-reset-ipq4019";
+ reg = <0x1800000 0x60000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
pinctrl: qcom,tlmm@1000000 {
compatible = "qcom,tlmm-ipq4019";
reg = <0x1000000 0x300000>;
--
2.26.2
