>-----Original Message-----
>From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
>Sent: Tuesday, September 1, 2020 3:03 PM
>To: u-boot@lists.denx.de; Priyanka Jain <priyanka.j...@nxp.com>
>Cc: Varun Sethi <v.se...@nxp.com>; Meenakshi Aggarwal
><meenakshi.aggar...@nxp.com>; Ioana Ciornei <ioana.cior...@nxp.com>;
>Qiang Zhao <qiang.z...@nxp.com>; Hui Song <hui.son...@nxp.com>;
>Manish Tomar <manish.to...@nxp.com>; Vikas Singh
><vikas.si...@nxp.com>
>Subject: [PATCH 2/2] armv8: lx2162aqds: Add support for LX2162AQDS
>platform
>
>From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
>
>This patch add base support for LX2162AQDS board.
>LX2162 is LX2160 based SoC, it has same die as of LX2160
>with different packaging.
No need to mention soc details. May be just mention that LX2162AQDS uses LX2162
SoC
>LX2162A support 4GB ddr memory, i2c, micro-click module, microSD card,
>serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
>interface,one usb 3.0 and serdes interface to support three x1gen3
>pcie interface.
>
Please check if board feature or soc feature
>Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
>Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
>Signed-off-by: hui.song <hui.son...@nxp.com>
>Signed-off-by: Manish Tomar <manish.to...@nxp.com>
>Signed-off-by: Vikas Singh <vikas.si...@nxp.com>
>Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
>---
> arch/arm/Kconfig | 12 +
> arch/arm/dts/Makefile | 6 +-
> arch/arm/dts/fsl-lx2160a-qds.dtsi | 16 +-
> arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 +
> arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 +
> arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 +
> arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++
> arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++
> arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 +
> arch/arm/dts/fsl-lx2162a-qds.dts | 36 +
> board/freescale/lx2160a/Kconfig | 16 +
> board/freescale/lx2160a/MAINTAINERS | 12 +-
> board/freescale/lx2160a/Makefile | 1 +
> board/freescale/lx2160a/eth_lx2162aqds.c | 974
>+++++++++++++++++++++++++
> board/freescale/lx2160a/lx2160a.c | 42 +-
> configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 +++
> configs/lx2162aqds_tfa_defconfig | 95 +++
> configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++
> include/configs/lx2160a_common.h | 2 +
> include/configs/lx2162aqds.h | 169 +++++
> 20 files changed, 1753 insertions(+), 23 deletions(-)
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
> create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
> create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
> create mode 100644 configs/lx2162aqds_tfa_defconfig
> create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
> create mode 100644 include/configs/lx2162aqds.h
>
>diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>index 80702c2..4bcbcc5 100644
>--- a/arch/arm/Kconfig
>+++ b/arch/arm/Kconfig
>@@ -1321,6 +1321,18 @@ config TARGET_LX2160AQDS
> is a high-performance development platform that supports the
> QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
>
>+config TARGET_LX2162AQDS
>+ bool "Support lx2162aqds"
>+ select ARCH_LX2160A
>+ select ARCH_MISC_INIT
>+ select ARM64
>+ select ARMV8_MULTIENTRY
>+ select ARCH_SUPPORT_TFABOOT
>+ select BOARD_LATE_INIT
>+ help
>+ Support for NXP LX2162AQDS platform.
>+ The lx2162aqds support is based on LX2160A Layerscape Architecture
>processor.
>+
> config TARGET_HIKEY
> bool "Support HiKey 96boards Consumer Edition Platform"
> select ARM64
>diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>index f8f5294..a34a56e 100644
>--- a/arch/arm/dts/Makefile
>+++ b/arch/arm/dts/Makefile
>@@ -409,7 +409,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
> fsl-lx2160a-qds-19-x-x.dtb \
> fsl-lx2160a-qds-19-11-x.dtb \
> fsl-lx2160a-qds-20-x-x.dtb \
>- fsl-lx2160a-qds-20-11-x.dtb
>+ fsl-lx2160a-qds-20-11-x.dtb \
>+ fsl-lx2162a-qds.dtb\
>+ fsl-lx2162a-qds-17-x.dtb\
>+ fsl-lx2162a-qds-18-x.dtb\
>+ fsl-lx2162a-qds-20-x.dtb
> dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
> fsl-ls1043a-qds-lpuart.dtb \
> fsl-ls1043a-rdb.dtb \
>diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-
>qds.dtsi
>index 96c9800..370f116 100644
>--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
>+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
>@@ -2,7 +2,7 @@
> /*
> * NXP LX2160AQDS common device tree source
> *
>- * Copyright 2018-2019 NXP
>+ * Copyright 2018-2020 NXP
> *
> */
>
>@@ -251,6 +251,20 @@
> };
> };
>
>+&fspi {
>+ status = "okay";
>+
>+ mt35xu512aba0: flash@0 {
>+ #address-cells = <1>;
>+ #size-cells = <1>;
>+ compatible = "jedec,spi-nor";
>+ spi-max-frequency = <50000000>;
>+ reg = <0>;
>+ spi-rx-bus-width = <8>;
>+ spi-tx-bus-width = <1>;
>+ };
>+};
>+
> &sata0 {
> status = "okay";
> };
>diff --git a/arch/arm/dts/fsl-lx2162a-qds-17-x.dts b/arch/arm/dts/fsl-lx2162a-
>qds-17-x.dts
>new file mode 100644
>index 0000000..8a8895f
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts
>@@ -0,0 +1,17 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source for SERDES protocol 17.x
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+/dts-v1/;
>+
>+#include "fsl-lx2162a-qds-sd1-17.dtsi"
>+
>+/ {
>+ model = "NXP Layerscape LX2160AQDS Board (DTS 17.x)";
>+ compatible = "fsl,lx2162aqds", "fsl,lx2160a";
>+
>+};
>diff --git a/arch/arm/dts/fsl-lx2162a-qds-18-x.dts b/arch/arm/dts/fsl-lx2162a-
>qds-18-x.dts
>new file mode 100644
>index 0000000..c28e5e2
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts
>@@ -0,0 +1,17 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source for SERDES protocol 18.x
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+/dts-v1/;
>+
>+#include "fsl-lx2162a-qds-sd1-18.dtsi"
>+
>+/ {
>+ model = "NXP Layerscape LX2160AQDS Board (DTS 18.x)";
>+ compatible = "fsl,lx2162aqds", "fsl,lx2160a";
>+
>+};
>diff --git a/arch/arm/dts/fsl-lx2162a-qds-20-x.dts b/arch/arm/dts/fsl-lx2162a-
>qds-20-x.dts
>new file mode 100644
>index 0000000..7882c76
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts
>@@ -0,0 +1,17 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source for SERDES protocol 20.x
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+/dts-v1/;
>+
>+#include "fsl-lx2162a-qds-sd1-20.dtsi"
>+
>+/ {
>+ model = "NXP Layerscape LX2160AQDS Board (DTS 20.x)";
>+ compatible = "fsl,lx2162aqds", "fsl,lx2160a";
>+
>+};
>diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-
>lx2162a-qds-sd1-17.dtsi
>new file mode 100644
>index 0000000..60f5a4e
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
>@@ -0,0 +1,58 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17
>+ *
>+ * Some assumptions are made:
>+ * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC
>3,4,5,6)
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+#include "fsl-lx2160a-qds.dtsi"
>+
>+&dpmac3 {
>+ status = "okay";
>+ phy-handle = <&inphi_phy0>;
>+ phy-connection-type = "25g-aui";
>+};
>+
>+&dpmac4 {
>+ status = "okay";
>+ phy-handle = <&inphi_phy1>;
>+ phy-connection-type = "25g-aui";
>+};
>+
>+&dpmac5 {
>+ status = "okay";
>+ phy-handle = <&inphi_phy2>;
>+ phy-connection-type = "25g-aui";
>+};
>+
>+&dpmac6 {
>+ status = "okay";
>+ phy-handle = <&inphi_phy3>;
>+ phy-connection-type = "25g-aui";
>+};
>+
>+&emdio1_slot1 {
>+ inphi_phy0: ethernet-phy@0 {
>+ compatible = "ethernet-phy-id0210.7440";
>+ reg = <0x0>;
>+ };
>+
>+ inphi_phy1: ethernet-phy@1 {
>+ compatible = "ethernet-phy-id0210.7440";
>+ reg = <0x1>;
>+ };
>+
>+ inphi_phy2: ethernet-phy@2 {
>+ compatible = "ethernet-phy-id0210.7440";
>+ reg = <0x2>;
>+ };
>+
>+ inphi_phy3: ethernet-phy@3 {
>+ compatible = "ethernet-phy-id0210.7440";
>+ reg = <0x3>;
>+ };
>+};
>diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-
>lx2162a-qds-sd1-18.dtsi
>new file mode 100644
>index 0000000..8e11b06
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
>@@ -0,0 +1,61 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18
>+ *
>+ * Some assumptions are made:
>+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
>+ * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC
>5,6)
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+#include "fsl-lx2160a-qds.dtsi"
>+
>+&dpmac3 {
>+ status = "okay";
>+ phy-handle = <&aquantia_phy1>;
>+ phy-connection-type = "usxgmii";
>+};
>+
>+&dpmac4 {
>+ status = "okay";
>+ phy-handle = <&aquantia_phy2>;
>+ phy-connection-type = "usxgmii";
>+};
>+
>+&dpmac5 {
>+ status = "okay";
>+ phy-handle = <&inphi_phy0>;
>+ phy-connection-type = "25g-aui";
>+};
>+
>+&dpmac6 {
>+ status = "okay";
>+ phy-handle = <&inphi_phy1>;
>+ phy-connection-type = "25g-aui";
>+};
>+
>+&emdio1_slot1 {
>+ aquantia_phy1: ethernet-phy@4 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x0>;
>+ };
>+
>+ aquantia_phy2: ethernet-phy@5 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x1>;
>+ };
>+};
>+
>+&emdio1_slot6 {
>+ inphi_phy0: ethernet-phy@0 {
>+ compatible = "ethernet-phy-id0210.7440";
>+ reg = <0x0>;
>+ };
>+
>+ inphi_phy1: ethernet-phy@1 {
>+ compatible = "ethernet-phy-id0210.7440";
>+ reg = <0x1>;
>+ };
>+};
>diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-
>lx2162a-qds-sd1-20.dtsi
>new file mode 100644
>index 0000000..faf4285
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
>@@ -0,0 +1,26 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20
>+ *
>+ * Some assumptions are made:
>+ * * Mezzanine card M8 is connected to IO SLOT1
>+ * (xlaui4 for DPMAC 1)
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+#include "fsl-lx2160a-qds.dtsi"
>+
>+&dpmac1 {
>+ status = "okay";
>+ phy-handle = <&cortina_phy1_0>;
>+ phy-connection-type = "xlaui4";
>+};
>+
>+&emdio1_slot1 {
>+ cortina_phy1_0: ethernet-phy@0 {
>+ compatible = "ethernet-phy-ieee802.3-c45";
>+ reg = <0x0>;
>+ };
>+};
>diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-
>qds.dts
>new file mode 100644
>index 0000000..2195607
>--- /dev/null
>+++ b/arch/arm/dts/fsl-lx2162a-qds.dts
>@@ -0,0 +1,36 @@
>+// SPDX-License-Identifier: GPL-2.0+ OR X11
>+/*
>+ * NXP LX2162AQDS device tree source
>+ *
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+/dts-v1/;
>+
>+#include "fsl-lx2160a-qds.dtsi"
>+
>+/ {
>+ model = "NXP Layerscape LX2162AQDS Board";
>+ compatible = "fsl,lx2162aqds", "fsl,lx2160a";
>+
>+ aliases {
>+ spi0 = &fspi;
>+
>+ pcie@3500000 {
>+ status = "disabled";
>+ };
>+
>+ pcie@3800000 {
>+ status = "disabled";
>+ };
>+
>+ pcie@3900000 {
>+ status = "disabled";
>+ };
>+ };
>+};
>+
>+&usb1 {
>+ status = "disabled";
>+};
>diff --git a/board/freescale/lx2160a/Kconfig
>b/board/freescale/lx2160a/Kconfig
>index 122a385..7556f7d 100644
>--- a/board/freescale/lx2160a/Kconfig
>+++ b/board/freescale/lx2160a/Kconfig
>@@ -32,3 +32,19 @@ config SYS_CONFIG_NAME
> source "board/freescale/common/Kconfig"
> endif
>
>+if TARGET_LX2162AQDS
>+
>+config SYS_BOARD
>+ default "lx2160a"
>+
>+config SYS_VENDOR
>+ default "freescale"
>+
>+config SYS_SOC
>+ default "fsl-layerscape"
>+
>+config SYS_CONFIG_NAME
>+ default "lx2162aqds"
>+
>+source "board/freescale/common/Kconfig"
>+endif
>diff --git a/board/freescale/lx2160a/MAINTAINERS
>b/board/freescale/lx2160a/MAINTAINERS
>index 9fe79c0..4a78155 100644
>--- a/board/freescale/lx2160a/MAINTAINERS
>+++ b/board/freescale/lx2160a/MAINTAINERS
>@@ -1,5 +1,6 @@
> LX2160ARDB BOARD
>-M: Priyanka Jain <priyanka.j...@nxp.com>
>+M: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
>+M: Priyanka Jain <priyanka.j...@nxp.com>
Why - and + of same text?
> S: Maintained
> F: board/freescale/lx2160a/
> F: include/configs/lx2160a_common.h
>@@ -14,6 +15,7 @@ S: Maintained
> F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
>
> LX2160AQDS BOARD
>+M: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> M: Pankaj Bansal <pankaj.ban...@nxp.com>
> S: Maintained
> F: board/freescale/lx2160a/eth_lx2160aqds.h
>@@ -25,3 +27,11 @@ LX2160AQDS_SECURE_BOOT BOARD
> M: Udit Agarwal <udit.agar...@nxp.com>
> S: Maintained
> F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
>+
>+LX2162AQDS BOARD
>+M: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
>+S: Maintained
>+F: board/freescale/lx2160a/eth_lx2162aqds.h
>+F: include/configs/lx2162aqds.h
>+F: configs/lx2162aqds_tfa_defconfig
>+F: arch/arm/dts/fsl-lx2162a-qds.dts
>diff --git a/board/freescale/lx2160a/Makefile
>b/board/freescale/lx2160a/Makefile
>index d1a621b..c9561bf 100644
>--- a/board/freescale/lx2160a/Makefile
>+++ b/board/freescale/lx2160a/Makefile
>@@ -8,3 +8,4 @@ obj-y += lx2160a.o
> obj-y += ddr.o
> obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
> obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
>+obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o
>diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c
>b/board/freescale/lx2160a/eth_lx2162aqds.c
>new file mode 100644
>index 0000000..309eea6
>--- /dev/null
>+++ b/board/freescale/lx2160a/eth_lx2162aqds.c
>@@ -0,0 +1,974 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2020 NXP
>+ *
>+ */
>+
>+#include <common.h>
>+#include <env.h>
>+#include <fdt_support.h>
>+#include <hwconfig.h>
>+#include <command.h>
>+#include <log.h>
>+#include <net.h>
>+#include <netdev.h>
>+#include <malloc.h>
>+#include <fsl_mdio.h>
>+#include <miiphy.h>
>+#include <phy.h>
>+#include <fm_eth.h>
>+#include <asm/io.h>
>+#include <exports.h>
>+#include <asm/arch/fsl_serdes.h>
>+#include <fsl-mc/fsl_mc.h>
>+#include <fsl-mc/ldpaa_wriop.h>
>+#include <linux/libfdt.h>
>+
>+#include "../common/qixis.h"
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+#ifndef CONFIG_DM_ETH
>+#define EMI_NONE 0
>+#define EMI1 1 /* Mdio Bus 1 */
>+#define EMI2 2 /* Mdio Bus 2 */
>+
>+#if defined(CONFIG_FSL_MC_ENET)
>+enum io_slot {
>+ IO_SLOT_NONE = 0,
>+ IO_SLOT_1,
>+ IO_SLOT_2,
>+ IO_SLOT_3,
>+ IO_SLOT_4,
>+ IO_SLOT_5,
>+ IO_SLOT_6,
>+ IO_SLOT_7,
>+ IO_SLOT_8,
>+ EMI1_RGMII1,
>+ EMI1_RGMII2,
>+ IO_SLOT_MAX
>+};
>+
>+struct lx2162a_qds_mdio {
>+ enum io_slot ioslot : 4;
>+ u8 realbusnum : 4;
>+ struct mii_dev *realbus;
>+};
>+
>+/* structure explaining the phy configuration on 8 lanes of a serdes*/
>+struct serdes_phy_config {
>+ u8 serdes; /* serdes protocol */
>+ struct phy_config {
>+ u8 dpmacid;
>+ /* -1 terminated array */
>+ int phy_address[WRIOP_MAX_PHY_NUM + 1];
>+ u8 mdio_bus;
>+ enum io_slot ioslot;
>+ } phy_config[SRDS_MAX_LANES];
>+};
>+
>+/* Table defining the phy configuration on 8 lanes of a serdes.
>+ * Various assumptions have been made while defining this table.
>+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
>+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
>+ * And also that this card is connected to IO Slot 1 (could have been
>connected
>+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
>+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G
>card
>+ * used in serdes1 protocol 19 (could have selected MDIO 2)
>+ * To override these settings "dpmac" environment variable can be used
>after
>+ * defining "dpmac_override" in hwconfig environment variable.
>+ * This table has limited serdes protocol entries. It can be expanded as per
>+ * requirement.
>+ */
>+/*********************************************************
>********
>+ | SERDES_1 PROTOCOL | IO_SLOT | CARD |
>+
>***********************************************************
>******
>+ | 2 | IO_SLOT_1 | M4-PCIE-SGMII |
>+ | 3 | IO_SLOT_1 | M11-USXGMII |
>+ | 15 | IO_SLOT_1 | M13-25G |
>+ | 17 | IO_SLOT_1 | M13-25G |
>+ | 18 | IO_SLOT_1 | M11-USXGMII |
>+ | | IO_SLOT_6 | M13-25G |
>+ | 20 | IO_SLOT_1 | M7-40G |
>+
>***********************************************************
>******
>+ */
>+static const struct serdes_phy_config serdes1_phy_config[] = {
>+ {1, {} },
>+ {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_1} } },
>+ {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
>+ EMI1, IO_SLOT_1} } },
>+ {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -
>1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_1} } },
>+ {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -
>1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_1} } },
>+ {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_1},
>+ {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_6},
>+ {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
>+ EMI1, IO_SLOT_6} } },
>+ {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
>+ EMI1, IO_SLOT_1} } }
>+};
>+
>+/*********************************************************
>********
>+ | SERDES_2 PROTOCOL | IO_SLOT | CARD |
>+
>***********************************************************
>******
>+ | 2 | IO_SLOT_7 | M4-PCIE-SGMII |
>+ | | IO_SLOT_8 | M4-PCIE-SGMII |
>+ | 3 | IO_SLOT_7 | M4-PCIE-SGMII |
>+ | | IO_SLOT_8 | M4-PCIE-SGMII |
>+ | 5 | IO_SLOT_7 | M4-PCIE-SGMII |
>+ | 10 | IO_SLOT_7 | M4-PCIE-SGMII |
>+ | | IO_SLOT_8 | M4-PCIE-SGMII |
>+ | 11 | IO_SLOT_7 | M4-PCIE-SGMII |
>+ | | IO_SLOT_8 | M4-PCIE-SGMII |
>+ | 12 | IO_SLOT_7 | M4-PCIE-SGMII |
>+ | | IO_SLOT_8 | M4-PCIE-SGMII |
>+
>***********************************************************
>******
>+ */
>+static const struct serdes_phy_config serdes2_phy_config[] = {
>+ {2, {} },
>+ {3, {} },
>+ {5, {} },
>+ {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7} } },
>+ {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_8},
>+ {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_8},
>+ {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_8} } },
>+ {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7},
>+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
>+ EMI1, IO_SLOT_7} } }
>+};
>+
>+static inline
>+const struct phy_config *get_phy_config(u8 serdes,
>+ const struct serdes_phy_config
>*table,
>+ u8 table_size)
>+{
>+ int i;
>+
>+ for (i = 0; i < table_size; i++) {
>+ if (table[i].serdes == serdes)
>+ return table[i].phy_config;
>+ }
>+
>+ return NULL;
>+}
>+
>+/* BRDCFG4 controls EMI routing for the board.
>+ * Bits Function
>+ * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
>+ * EMI1 00= On-board PHY #1
>+ * 01= On-board PHY #2
>+ * 10= (reserved)
>+ * 11= Slots 1..8 multiplexer and translator.
>+ * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
>+ * EMI1X 000= Slot #1
>+ * 001= Slot #2
>+ * 010= Slot #3
>+ * 011= Slot #4
>+ * 100= Slot #5
>+ * 101= Slot #6
>+ * 110= Slot #7
>+ * 111= Slot #8
>+ * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
>+ * EMI2 000= Slot #1 (secondary EMI)
>+ * 001= Slot #2 (secondary EMI)
>+ * 010= Slot #3 (secondary EMI)
>+ * 011= Slot #4 (secondary EMI)
>+ * 100= Slot #5 (secondary EMI)
>+ * 101= Slot #6 (secondary EMI)
>+ * 110= Slot #7 (secondary EMI)
>+ * 111= Slot #8 (secondary EMI)
>+ */
>+static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot
>ioslot)
>+{
>+ switch (realbusnum) {
>+ case EMI1:
>+ switch (ioslot) {
>+ case EMI1_RGMII1:
>+ return 0;
>+ case EMI1_RGMII2:
>+ return 0x40;
>+ default:
>+ return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) |
>0xC0);
>+ }
>+ break;
>+ case EMI2:
>+ return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
>+ default:
>+ return -1;
>+ }
>+}
>+
>+static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
>+{
>+ u8 brdcfg4, mux_val, reg;
>+
>+ brdcfg4 = QIXIS_READ(brdcfg[4]);
>+ reg = brdcfg4;
>+ mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv-
>>ioslot);
>+
>+ switch (priv->realbusnum) {
>+ case EMI1:
>+ brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
>+ brdcfg4 |= mux_val;
>+ break;
>+ case EMI2:
>+ brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
>+ brdcfg4 |= mux_val;
>+ break;
>+ }
>+
>+ if (brdcfg4 ^ reg)
>+ QIXIS_WRITE(brdcfg[4], brdcfg4);
>+}
>+
>+static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
>+ int devad, int regnum)
>+{
>+ struct lx2162a_qds_mdio *priv = bus->priv;
>+
>+ lx2162a_qds_mux_mdio(priv);
>+
>+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
>+}
>+
>+static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
>+ int regnum, u16 value)
>+{
>+ struct lx2162a_qds_mdio *priv = bus->priv;
>+
>+ lx2162a_qds_mux_mdio(priv);
>+
>+ return priv->realbus->write(priv->realbus, addr, devad, regnum,
>value);
>+}
>+
>+static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
>+{
>+ struct lx2162a_qds_mdio *priv = bus->priv;
>+
>+ return priv->realbus->reset(priv->realbus);
>+}
>+
>+static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot
>ioslot)
>+{
>+ struct lx2162a_qds_mdio *pmdio;
>+ struct mii_dev *bus;
>+ /*should be within MDIO_NAME_LEN*/
>+ char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
>+
>+ if (realbusnum == EMI2) {
>+ if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
>+ printf("invalid ioslot %d\n", ioslot);
>+ return NULL;
>+ }
>+ } else if (realbusnum == EMI1) {
>+ if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
>+ printf("invalid ioslot %d\n", ioslot);
>+ return NULL;
>+ }
>+ } else {
>+ printf("not supported real mdio bus %d\n", realbusnum);
>+ return NULL;
>+ }
>+
>+ if (ioslot == EMI1_RGMII1)
>+ strcpy(dummy_mdio_name,
>"LX2162A_QDS_MDIO1_RGMII1");
>+ else if (ioslot == EMI1_RGMII2)
>+ strcpy(dummy_mdio_name,
>"LX2162A_QDS_MDIO1_RGMII2");
>+ else
>+ sprintf(dummy_mdio_name,
>"LX2162A_QDS_MDIO%d_IOSLOT%d",
>+ realbusnum, ioslot);
>+ bus = miiphy_get_dev_by_name(dummy_mdio_name);
>+
>+ if (bus)
>+ return bus;
>+
>+ bus = mdio_alloc();
>+ if (!bus) {
>+ printf("Failed to allocate %s bus\n", dummy_mdio_name);
>+ return NULL;
>+ }
>+
>+ pmdio = malloc(sizeof(*pmdio));
>+ if (!pmdio) {
>+ printf("Failed to allocate %s private data\n",
>dummy_mdio_name);
>+ free(bus);
>+ return NULL;
>+ }
>+
>+ switch (realbusnum) {
>+ case EMI1:
>+ pmdio->realbus =
>+
>miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
>+ break;
>+ case EMI2:
>+ pmdio->realbus =
>+
>miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
>+ break;
>+ }
>+
>+ if (!pmdio->realbus) {
>+ printf("No real mdio bus num %d found\n", realbusnum);
>+ free(bus);
>+ free(pmdio);
>+ return NULL;
>+ }
>+
>+ pmdio->realbusnum = realbusnum;
>+ pmdio->ioslot = ioslot;
>+ bus->read = lx2162a_qds_mdio_read;
>+ bus->write = lx2162a_qds_mdio_write;
>+ bus->reset = lx2162a_qds_mdio_reset;
>+ strcpy(bus->name, dummy_mdio_name);
>+ bus->priv = pmdio;
>+
>+ if (!mdio_register(bus))
>+ return bus;
>+
>+ printf("No bus with name %s\n", dummy_mdio_name);
>+ free(bus);
>+ free(pmdio);
>+ return NULL;
>+}
>+
>+static inline void do_phy_config(const struct phy_config *phy_config)
>+{
>+ struct mii_dev *bus;
>+ int i, phy_num, phy_address;
>+
>+ for (i = 0; i < SRDS_MAX_LANES; i++) {
>+ if (!phy_config[i].dpmacid)
>+ continue;
>+
>+ for (phy_num = 0;
>+ phy_num < ARRAY_SIZE(phy_config[i].phy_address);
>+ phy_num++) {
>+ phy_address = phy_config[i].phy_address[phy_num];
>+ if (phy_address == -1)
>+ break;
>+ wriop_set_phy_address(phy_config[i].dpmacid,
>+ phy_num, phy_address);
>+ }
>+ /*Register the muxing front-ends to the MDIO buses*/
>+ bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
>+ phy_config[i].ioslot);
>+ if (!bus)
>+ printf("could not get bus for mdio %d ioslot %d\n",
>+ phy_config[i].mdio_bus,
>+ phy_config[i].ioslot);
>+ else
>+ wriop_set_mdio(phy_config[i].dpmacid, bus);
>+ }
>+}
>+
>+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
>+ char *env_dpmac)
>+{
>+ const char *ret;
>+ size_t len;
>+ u8 realbusnum, ioslot;
>+ struct mii_dev *bus;
>+ int phy_num;
>+ char *phystr = "phy00";
>+
>+ /*search phy in dpmac arg*/
>+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++)
>{
>+ sprintf(phystr, "phy%d", phy_num + 1);
>+ ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len,
>env_dpmac);
>+ if (!ret) {
>+ /*look for phy instead of phy1*/
>+ if (!phy_num)
>+ ret = hwconfig_subarg_f(arg_dpmacid, "phy",
>+ &len, env_dpmac);
>+ if (!ret)
>+ continue;
>+ }
>+
>+ if (len != 4 || strncmp(ret, "0x", 2))
>+ printf("invalid phy format in %s variable.\n"
>+ "specify phy%d for %s in hex format e.g. 0x12\n",
>+ env_dpmac, phy_num + 1, arg_dpmacid);
>+ else
>+ wriop_set_phy_address(dpmac, phy_num,
>+ simple_strtoul(ret, NULL, 16));
>+ }
>+
>+ /*search mdio in dpmac arg*/
>+ ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
>+ if (ret)
>+ realbusnum = *ret - '0';
>+ else
>+ realbusnum = EMI_NONE;
>+
>+ if (realbusnum) {
>+ /*search io in dpmac arg*/
>+ ret = hwconfig_subarg_f(arg_dpmacid, "io", &len,
>env_dpmac);
>+ if (ret)
>+ ioslot = *ret - '0';
>+ else
>+ ioslot = IO_SLOT_NONE;
>+ /*Register the muxing front-ends to the MDIO buses*/
>+ bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
>+ if (!bus)
>+ printf("could not get bus for mdio %d ioslot %d\n",
>+ realbusnum, ioslot);
>+ else
>+ wriop_set_mdio(dpmac, bus);
>+ }
>+}
>+
>+#endif
>+#endif /* !CONFIG_DM_ETH */
>+
>+int board_eth_init(struct bd_info *bis)
>+{
>+#ifndef CONFIG_DM_ETH
>+#if defined(CONFIG_FSL_MC_ENET)
>+ struct memac_mdio_info mdio_info;
>+ struct memac_mdio_controller *regs;
>+ int i;
>+ const char *ret;
>+ char *env_dpmac;
>+ char dpmacid[] = "dpmac00", srds[] = "00_00_00";
>+ size_t len;
>+ struct mii_dev *bus;
>+ const struct phy_config *phy_config;
>+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>+ u32 srds_s1, srds_s2;
>+
>+ srds_s1 = in_le32(&gur->rcwsr[28]) &
>+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
>+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
>+
>+ srds_s2 = in_le32(&gur->rcwsr[28]) &
>+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
>+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
>+
>+ sprintf(srds, "%d_%d", srds_s1, srds_s2);
>+
>+ regs = (struct memac_mdio_controller
>*)CONFIG_SYS_FSL_WRIOP1_MDIO1;
>+ mdio_info.regs = regs;
>+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
>+
>+ /*Register the EMI 1*/
>+ fm_memac_mdio_init(bis, &mdio_info);
>+
>+ regs = (struct memac_mdio_controller
>*)CONFIG_SYS_FSL_WRIOP1_MDIO2;
>+ mdio_info.regs = regs;
>+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
>+
>+ /*Register the EMI 2*/
>+ fm_memac_mdio_init(bis, &mdio_info);
>+
>+ /* "dpmac" environment variable can be used after
>+ * defining "dpmac_override" in hwconfig environment variable.
>+ */
>+ if (hwconfig("dpmac_override")) {
>+ env_dpmac = env_get("dpmac");
>+ if (env_dpmac) {
>+ ret = hwconfig_arg_f("srds", &len, env_dpmac);
>+ if (ret) {
>+ if (strncmp(ret, srds, strlen(srds))) {
>+ printf("SERDES configuration
>changed.\n"
>+ "previous: %.*s, current: %s.\n"
>+ "update dpmac variable.\n",
>+ (int)len, ret, srds);
>+ }
>+ } else {
>+ printf("SERDES configuration not found.\n"
>+ "Please add srds:%s in dpmac variable\n",
>+ srds);
>+ }
>+
>+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS;
>i++) {
>+ /* Look for dpmac1 to dpmac24(current max)
>arg
>+ * in dpmac environment variable
>+ */
>+ sprintf(dpmacid, "dpmac%d", i);
>+ ret = hwconfig_arg_f(dpmacid, &len,
>env_dpmac);
>+ if (ret)
>+ do_dpmac_config(i, dpmacid,
>env_dpmac);
>+ }
>+ } else {
>+ printf("Warning: environment dpmac not found.\n"
>+ "DPAA network interfaces may not work\n");
>+ }
>+ } else {
>+ /*Look for phy config for serdes1 in phy config table*/
>+ phy_config = get_phy_config(srds_s1, serdes1_phy_config,
>+ ARRAY_SIZE(serdes1_phy_config));
>+ if (!phy_config) {
>+ printf("%s WRIOP: Unsupported SerDes1 Protocol
>%d\n",
>+ __func__, srds_s1);
>+ } else {
>+ do_phy_config(phy_config);
>+ }
>+ phy_config = get_phy_config(srds_s2, serdes2_phy_config,
>+ ARRAY_SIZE(serdes2_phy_config));
>+ if (!phy_config) {
>+ printf("%s WRIOP: Unsupported SerDes2 Protocol
>%d\n",
>+ __func__, srds_s2);
>+ } else {
>+ do_phy_config(phy_config);
>+ }
>+ }
>+
>+ if (wriop_get_enet_if(WRIOP1_DPMAC17) ==
>PHY_INTERFACE_MODE_RGMII_ID) {
>+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
>RGMII_PHY_ADDR1);
>+ bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
>+ if (!bus)
>+ printf("could not get bus for RGMII1\n");
>+ else
>+ wriop_set_mdio(WRIOP1_DPMAC17, bus);
>+ }
>+
>+ if (wriop_get_enet_if(WRIOP1_DPMAC18) ==
>PHY_INTERFACE_MODE_RGMII_ID) {
>+ wriop_set_phy_address(WRIOP1_DPMAC18, 0,
>RGMII_PHY_ADDR2);
>+ bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
>+ if (!bus)
>+ printf("could not get bus for RGMII2\n");
>+ else
>+ wriop_set_mdio(WRIOP1_DPMAC18, bus);
>+ }
>+
>+ cpu_eth_init(bis);
>+#endif /* CONFIG_FMAN_ENET */
>+#endif /* !CONFIG_DM_ETH */
>+
>+#ifdef CONFIG_PHY_AQUANTIA
>+ /*
>+ * Export functions to be used by AQ firmware
>+ * upload application
>+ */
>+ gd->jt->strcpy = strcpy;
>+ gd->jt->mdelay = mdelay;
>+ gd->jt->mdio_get_current_dev = mdio_get_current_dev;
>+ gd->jt->phy_find_by_mask = phy_find_by_mask;
>+ gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
>+ gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
>+#endif
>+
>+#ifdef CONFIG_DM_ETH
>+ return 0;
>+#else
>+ return pci_eth_init(bis);
>+#endif
>+}
>+
>+#if defined(CONFIG_RESET_PHY_R)
>+void reset_phy(void)
>+{
>+#if defined(CONFIG_FSL_MC_ENET)
>+ mc_env_boot();
>+#endif
>+}
>+#endif /* CONFIG_RESET_PHY_R */
>+
>+#ifndef CONFIG_DM_ETH
>+#if defined(CONFIG_FSL_MC_ENET)
>+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int
>node_phandle)
>+{
>+ int offset;
>+ int ret;
>+ char dpmac_str[] = "dpmacs@00";
>+ const char *phy_string;
>+
>+ offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
>+
>+ if (offset < 0)
>+ offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
>+
>+ if (offset < 0) {
>+ printf("dpmacs node not found in device tree\n");
>+ return offset;
>+ }
>+
>+ sprintf(dpmac_str, "dpmac@%x", dpmac_id);
>+ debug("dpmac_str = %s\n", dpmac_str);
>+
>+ offset = fdt_subnode_offset(fdt, offset, dpmac_str);
>+ if (offset < 0) {
>+ printf("%s node not found in device tree\n", dpmac_str);
>+ return offset;
>+ }
>+
>+ phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
>+ if (is_backplane_mode(phy_string)) {
>+ /* Backplane KR mode: skip fixups */
>+ printf("Interface %d in backplane KR mode\n", dpmac_id);
>+ return 0;
>+ }
>+
>+ ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
>+ if (ret)
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+
>+ phy_string =
>phy_string_for_interface(wriop_get_enet_if(dpmac_id));
>+ ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
>+ phy_string);
>+ if (ret)
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+
>+ return ret;
>+}
>+
>+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
>+{
>+ char mdio_ioslot_str[] = "mdio@00";
>+ struct lx2162a_qds_mdio *priv;
>+ u64 reg;
>+ u32 phandle;
>+ int offset, mux_val;
>+
>+ /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
>+ if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
>+ strlen("LX2162A_QDS_MDIO")))
>+ return -1;
>+
>+ /*Get the real MDIO bus num and ioslot info from bus's priv data*/
>+ priv = mii_dev->priv;
>+
>+ debug("real_bus_num = %d, ioslot = %d\n",
>+ priv->realbusnum, priv->ioslot);
>+
>+ if (priv->realbusnum == EMI1)
>+ reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
>+ else
>+ reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
>+
>+ offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-
>mdio", reg);
>+ if (offset < 0) {
>+ printf("mdio@%llx node not found in device tree\n", reg);
>+ return offset;
>+ }
>+
>+ phandle = fdt_get_phandle(fdt, offset);
>+ phandle = cpu_to_fdt32(phandle);
>+ offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
>+ &phandle, 4);
>+ if (offset < 0) {
>+ printf("mdio-mux-%d node not found in device tree\n",
>+ priv->realbusnum == EMI1 ? 1 : 2);
>+ return offset;
>+ }
>+
>+ mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv-
>>ioslot);
>+ if (priv->realbusnum == EMI1)
>+ mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
>+ else
>+ mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
>+ sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
>+
>+ offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
>+ if (offset < 0) {
>+ printf("%s node not found in device tree\n", mdio_ioslot_str);
>+ return offset;
>+ }
>+
>+ return offset;
>+}
>+
>+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int
>*subnodeoffset,
>+ struct phy_device *phy_dev, int phandle)
>+{
>+ char phy_node_name[] = "ethernet-phy@00";
>+ char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
>+ int ret;
>+
>+ sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
>+ debug("phy_node_name = %s\n", phy_node_name);
>+
>+ *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
>+ if (*subnodeoffset <= 0) {
>+ printf("Could not add subnode %s inside node %s err = %s\n",
>+ phy_node_name, fdt_get_name(fdt, offset, NULL),
>+ fdt_strerror(*subnodeoffset));
>+ return *subnodeoffset;
>+ }
>+
>+ sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
>+ phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
>+ debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
>+
>+ ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
>+ phy_id_compatible_str);
>+ if (ret) {
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+ goto out;
>+ }
>+
>+ if (phy_dev->is_c45) {
>+ ret = fdt_appendprop_string(fdt, *subnodeoffset,
>"compatible",
>+ "ethernet-phy-ieee802.3-c45");
>+ if (ret) {
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+ goto out;
>+ }
>+ } else {
>+ ret = fdt_appendprop_string(fdt, *subnodeoffset,
>"compatible",
>+ "ethernet-phy-ieee802.3-c22");
>+ if (ret) {
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+ goto out;
>+ }
>+ }
>+
>+ ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
>+ if (ret) {
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+ goto out;
>+ }
>+
>+ ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
>+ if (ret) {
>+ printf("%d@%s %d\n", __LINE__, __func__, ret);
>+ goto out;
>+ }
>+
>+out:
>+ if (ret)
>+ fdt_del_node(fdt, *subnodeoffset);
>+
>+ return ret;
>+}
>+
>+#define is_rgmii(dpmac_id) \
>+ wriop_get_enet_if((dpmac_id)) ==
>PHY_INTERFACE_MODE_RGMII_ID
>+
>+int fdt_fixup_board_phy(void *fdt)
>+{
>+ int fpga_offset, offset, subnodeoffset;
>+ struct mii_dev *mii_dev;
>+ struct list_head *mii_devs, *entry;
>+ int ret, dpmac_id, phandle, i;
>+ struct phy_device *phy_dev;
>+ char ethname[ETH_NAME_LEN];
>+ phy_interface_t phy_iface;
>+
>+ ret = 0;
>+ /* we know FPGA is connected to i2c0, therefore search path directly,
>+ * instead of compatible property, as it saves time
>+ */
>+ fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
>+
>+ if (fpga_offset < 0)
>+ fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
>+
>+ if (fpga_offset < 0) {
>+ printf("i2c@2000000/fpga node not found in device tree\n");
>+ return fpga_offset;
>+ }
>+
>+ phandle = fdt_alloc_phandle(fdt);
>+ mii_devs = mdio_get_list_head();
>+
>+ list_for_each(entry, mii_devs) {
>+ mii_dev = list_entry(entry, struct mii_dev, link);
>+ debug("mii_dev name : %s\n", mii_dev->name);
>+ offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
>+ if (offset < 0)
>+ continue;
>+
>+ // Look for phy devices attached to MDIO bus muxing front
>end
>+ // and create their entries with compatible being the device id
>+ for (i = 0; i < PHY_MAX_ADDR; i++) {
>+ phy_dev = mii_dev->phymap[i];
>+ if (!phy_dev)
>+ continue;
>+
>+ // TODO: use sscanf instead of loop
>+ dpmac_id = WRIOP1_DPMAC1;
>+ while (dpmac_id < NUM_WRIOP_PORTS) {
>+ phy_iface = wriop_get_enet_if(dpmac_id);
>+ snprintf(ethname, ETH_NAME_LEN,
>"DPMAC%d@%s",
>+ dpmac_id,
>+ phy_string_for_interface(phy_iface));
>+ if (strcmp(ethname, phy_dev->dev->name)
>== 0)
>+ break;
>+ dpmac_id++;
>+ }
>+ if (dpmac_id == NUM_WRIOP_PORTS)
>+ continue;
>+
>+ if ((dpmac_id == 17 || dpmac_id == 18) &&
>+ is_rgmii(dpmac_id))
>+ continue;
>+
>+ ret = fdt_create_phy_node(fdt, offset, i,
>+ &subnodeoffset,
>+ phy_dev, phandle);
>+ if (ret)
>+ break;
>+
>+ ret = fdt_fixup_dpmac_phy_handle(fdt,
>+ dpmac_id, phandle);
>+ if (ret) {
>+ fdt_del_node(fdt, subnodeoffset);
>+ break;
>+ }
>+ /* calculate offset again as new node addition may
>have
>+ * changed offset;
>+ */
>+ offset = fdt_get_ioslot_offset(fdt, mii_dev,
>+ fpga_offset);
>+ phandle++;
>+ }
>+
>+ if (ret)
>+ break;
>+ }
>+
>+ return ret;
>+}
>+#endif // CONFIG_FSL_MC_ENET
>+#endif
>+
>+#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
>+
>+/* Structure to hold SERDES protocols supported in case of
>+ * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
>+ *
>+ * @serdes_block: the index of the SERDES block
>+ * @serdes_protocol: the decimal value of the protocol supported
>+ * @dts_needed: DTS notes describing the current configuration are needed
>+ *
>+ * When dts_needed is true, the board_fit_config_name_match() function
>+ * will try to exactly match the current configuration of the block with a DTS
>+ * name provided.
>+ */
>+static struct serdes_configuration {
>+ u8 serdes_block;
>+ u32 serdes_protocol;
>+ bool dts_needed;
>+} supported_protocols[] = {
>+ /* Serdes block #1 */
>+ {1, 2, true},
>+ {1, 3, true},
>+ {1, 15, true},
>+ {1, 17, true},
>+ {1, 18, true},
>+ {1, 20, true},
>+
>+ /* Serdes block #2 */
>+ {2, 2, false},
>+ {2, 3, false},
>+ {2, 5, false},
>+ {2, 10, false},
>+ {2, 11, true},
>+ {2, 12, true},
>+};
>+
>+#define SUPPORTED_SERDES_PROTOCOLS
>ARRAY_SIZE(supported_protocols)
>+
>+static bool protocol_supported(u8 serdes_block, u32 protocol)
>+{
>+ struct serdes_configuration serdes_conf;
>+ int i;
>+
>+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
>+ serdes_conf = supported_protocols[i];
>+ if (serdes_conf.serdes_block == serdes_block &&
>+ serdes_conf.serdes_protocol == protocol)
>+ return true;
>+ }
>+
>+ return false;
>+}
>+
>+static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
>+{
>+ struct serdes_configuration serdes_conf;
>+ int i;
>+
>+ for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
>+ serdes_conf = supported_protocols[i];
>+ if (serdes_conf.serdes_block == serdes_block &&
>+ serdes_conf.serdes_protocol == protocol) {
>+ if (serdes_conf.dts_needed == true)
>+ sprintf(str, "%u", protocol);
>+ else
>+ sprintf(str, "x");
>+ return;
>+ }
>+ }
>+}
>+
>+int board_fit_config_name_match(const char *name)
>+{
>+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
>+ u32 rcw_status = in_le32(&gur->rcwsr[28]);
>+ char srds_s1_str[2], srds_s2_str[2];
>+ u32 srds_s1, srds_s2;
>+ char expected_dts[100];
>+
>+ srds_s1 = rcw_status &
>FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
>+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
>+
>+ srds_s2 = rcw_status &
>FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
>+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
>+
>+ /* Check for supported protocols. The default DTS will be used
>+ * in this case
>+ */
>+ if (!protocol_supported(1, srds_s1) ||
>+ !protocol_supported(2, srds_s2))
>+ return -1;
>+
>+ get_str_protocol(1, srds_s1, srds_s1_str);
>+ get_str_protocol(2, srds_s2, srds_s2_str);
>+
>+ sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s",
>+ srds_s1_str, srds_s2_str);
>+
>+ if (!strcmp(name, expected_dts))
>+ return 0;
>+
>+ return -1;
>+}
>+#endif
>diff --git a/board/freescale/lx2160a/lx2160a.c
>b/board/freescale/lx2160a/lx2160a.c
>index ace2a19..a5754a5 100644
>--- a/board/freescale/lx2160a/lx2160a.c
>+++ b/board/freescale/lx2160a/lx2160a.c
>@@ -37,7 +37,7 @@
> #include "../common/emc2305.h"
> #endif
>
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
> #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
> #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
>@@ -47,7 +47,7 @@
> #define SDHC1_BASE_PMUX_DSPI 2
> #define SDHC2_BASE_PMUX_DSPI 2
> #define IIC5_PMUX_SPI3 3
>-#endif /* CONFIG_TARGET_LX2160AQDS */
>+#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS
>*/
>
> DECLARE_GLOBAL_DATA_PTR;
>
>@@ -191,7 +191,7 @@ int board_fix_fdt(void *fdt)
> }
> #endif
>
>-#if defined(CONFIG_TARGET_LX2160AQDS)
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> void esdhc_dspi_status_fixup(void *blob)
> {
> const char esdhc0_path[] = "/soc/esdhc@2140000";
>@@ -259,7 +259,7 @@ void esdhc_dspi_status_fixup(void *blob)
>
> int esdhc_status_fixup(void *blob, const char *compat)
> {
>-#if defined(CONFIG_TARGET_LX2160AQDS)
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> /* Enable esdhc and dspi DT nodes based on RCW fields */
> esdhc_dspi_status_fixup(blob);
> #else
>@@ -297,7 +297,7 @@ int checkboard(void)
> enum boot_src src = get_boot_src();
> char buf[64];
> u8 sw;
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> int clock;
> static const char *const freq[] = {"100", "125", "156.25",
> "161.13", "322.26", "", "", "",
>@@ -306,7 +306,7 @@ int checkboard(void)
> #endif
>
> cpu_name(buf);
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> printf("Board: %s-QDS, ", buf);
> #else
> printf("Board: %s-RDB, ", buf);
>@@ -339,7 +339,13 @@ int checkboard(void)
> break;
> }
> }
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160ARDB)
>+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
>+
>+ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 =
>161.13MHz\n");
>+ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
>+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
>+#else
> printf("FPGA: v%d (%s), build %d",
> (int)QIXIS_READ(scver), qixis_read_tag(buf),
> (int)qixis_read_minor());
>@@ -350,31 +356,27 @@ int checkboard(void)
> sw = QIXIS_READ(brdcfg[2]);
> clock = sw >> 4;
> printf("Clock1 = %sMHz ", freq[clock]);
>+#if defined(CONFIG_TARGET_LX2160AQDS)
> clock = sw & 0x0f;
> printf("Clock2 = %sMHz", freq[clock]);
>-
>+#endif
> sw = QIXIS_READ(brdcfg[3]);
> puts("\nSERDES2 Reference : ");
> clock = sw >> 4;
> printf("Clock1 = %sMHz ", freq[clock]);
> clock = sw & 0x0f;
>- printf("Clock2 = %sMHz", freq[clock]);
>-
>+ printf("Clock2 = %sMHz\n", freq[clock]);
>+#if defined(CONFIG_TARGET_LX2160AQDS)
> sw = QIXIS_READ(brdcfg[12]);
>- puts("\nSERDES3 Reference : ");
>+ puts("SERDES3 Reference : ");
> clock = sw >> 4;
> printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
>-#else
>- printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
>-
>- puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 =
>161.13MHz\n");
>- puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
>- puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
>+#endif
> #endif
> return 0;
> }
>
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> /*
> * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
> */
>@@ -562,7 +564,7 @@ int config_board_mux(void)
>
> unsigned long get_board_sys_clk(void)
> {
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
>
> switch (sysclk_conf & 0x03) {
>@@ -581,7 +583,7 @@ unsigned long get_board_sys_clk(void)
>
> unsigned long get_board_ddr_clk(void)
> {
>-#ifdef CONFIG_TARGET_LX2160AQDS
>+#if defined(CONFIG_TARGET_LX2160AQDS) ||
>defined(CONFIG_TARGET_LX2162AQDS)
> u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
>
> switch ((ddrclk_conf & 0x30) >> 4) {
Please update REAMDE of board in board patch and README of SoC in Soc patch
>diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
>b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
>new file mode 100644
>index 0000000..065f6a1
>--- /dev/null
>+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
>@@ -0,0 +1,97 @@
>+CONFIG_ARM=y
>+CONFIG_TARGET_LX2162AQDS=y
>+CONFIG_TFABOOT=y
>+CONFIG_SYS_TEXT_BASE=0x82000000
>+CONFIG_SYS_MALLOC_F_LEN=0x6000
>+CONFIG_NXP_ESBC=y
>+CONFIG_ENV_SIZE=0x2000
>+CONFIG_ENV_SECT_SIZE=0x20000
>+CONFIG_ENV_OFFSET=0x500000
>+CONFIG_FSPI_AHB_EN_4BYTE=y
>+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
>+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
>+CONFIG_AHCI=y
>+CONFIG_NR_DRAM_BANKS=3
>+CONFIG_FIT_VERBOSE=y
>+CONFIG_OF_BOARD_SETUP=y
>+CONFIG_OF_STDOUT_VIA_ALIAS=y
>+CONFIG_USE_BOOTARGS=y
>+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0
>earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000
>default_hugepagesz=1024m hugepagesz=1024m hugepages=2
>pci=pcie_bus_perf"
>+# CONFIG_USE_BOOTCOMMAND is not set
>+CONFIG_MISC_INIT_R=y
>+CONFIG_BOARD_EARLY_INIT_R=y
>+CONFIG_CMD_GREPENV=y
>+CONFIG_CMD_EEPROM=y
>+CONFIG_CMD_DM=y
>+CONFIG_CMD_GPT=y
>+CONFIG_CMD_GPIO=y
>+CONFIG_CMD_I2C=y
>+CONFIG_CMD_MMC=y
>+CONFIG_CMD_PCI=y
>+CONFIG_CMD_SF=y
>+CONFIG_CMD_USB=y
>+CONFIG_CMD_WDT=y
>+CONFIG_CMD_CACHE=y
>+CONFIG_MP=y
>+CONFIG_OF_CONTROL=y
>+CONFIG_OF_BOARD_FIXUP=y
>+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
>+CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-
>20-x"
>+CONFIG_MULTI_DTB_FIT=y
>+CONFIG_ENV_OVERWRITE=y
>+CONFIG_ENV_IS_IN_MMC=y
>+CONFIG_ENV_IS_IN_SPI_FLASH=y
>+CONFIG_ENV_ADDR=0x20500000
>+CONFIG_NET_RANDOM_ETHADDR=y
>+CONFIG_DM=y
>+CONFIG_SATA_CEVA=y
>+CONFIG_DM_MMC=y
>+CONFIG_FSL_ESDHC=y
>+CONFIG_MTD=y
>+CONFIG_DM_SPI_FLASH=y
>+CONFIG_SPI_FLASH_EON=y
>+CONFIG_SPI_FLASH_SST=y
>+CONFIG_SPI_FLASH=y
>+CONFIG_SPI_FLASH_STMICRO=y
>+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
>+CONFIG_PHYLIB=y
>+CONFIG_PHY_AQUANTIA=y
>+CONFIG_PHY_CORTINA=y
>+CONFIG_PHY_REALTEK=y
>+CONFIG_PHY_VITESSE=y
>+CONFIG_DM_ETH=y
>+CONFIG_DM_MDIO=y
>+CONFIG_DM_MDIO_MUX=y
>+CONFIG_E1000=y
>+CONFIG_MDIO_MUX_I2CREG=y
>+CONFIG_FSL_LS_MDIO=y
>+CONFIG_PCI=y
>+CONFIG_DM_PCI=y
>+CONFIG_DM_PCI_COMPAT=y
>+CONFIG_PCIE_LAYERSCAPE_RC=y
>+CONFIG_DM_SCSI=y
>+CONFIG_DM_SERIAL=y
>+CONFIG_SPI=y
>+CONFIG_DM_SPI=y
>+CONFIG_FSL_DSPI=y
>+CONFIG_NXP_FSPI=y
>+CONFIG_USB=y
>+CONFIG_DM_USB=y
>+CONFIG_USB_XHCI_HCD=y
>+CONFIG_USB_XHCI_DWC3=y
>+CONFIG_WDT=y
>+CONFIG_WDT_SBSA=y
>+CONFIG_RSA=y
>+CONFIG_SPL_RSA=y
>+CONFIG_RSA_SOFTWARE_EXP=y
>+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
>+CONFIG_GIC_V3_ITS=y
>+CONFIG_DM_I2C=y
>+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
>+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
>+CONFIG_DM_RTC=y
>+CONFIG_DM_GPIO=y
>+CONFIG_CMD_DATE=y
>+CONFIG_RTC_PCF2127=y
>+CONFIG_I2C_MUX=y
>+CONFIG_I2C_MUX_PCA954x=y
>diff --git a/configs/lx2162aqds_tfa_defconfig
>b/configs/lx2162aqds_tfa_defconfig
>new file mode 100644
>index 0000000..33ca543
>--- /dev/null
>+++ b/configs/lx2162aqds_tfa_defconfig
>@@ -0,0 +1,95 @@
>+CONFIG_ARM=y
>+CONFIG_TARGET_LX2162AQDS=y
>+CONFIG_SYS_TEXT_BASE=0x82000000
>+CONFIG_SYS_MALLOC_F_LEN=0x6000
>+CONFIG_ENV_SIZE=0x2000
>+CONFIG_ENV_SECT_SIZE=0x20000
>+CONFIG_ENV_OFFSET=0x500000
>+CONFIG_FSPI_AHB_EN_4BYTE=y
>+CONFIG_TFABOOT=y
>+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
>+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
>+CONFIG_AHCI=y
>+CONFIG_NR_DRAM_BANKS=3
>+CONFIG_FIT_VERBOSE=y
>+CONFIG_OF_BOARD_SETUP=y
>+CONFIG_OF_STDOUT_VIA_ALIAS=y
>+CONFIG_BOOTDELAY=10
>+CONFIG_USE_BOOTARGS=y
>+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0
>earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000
>default_hugepagesz=1024m hugepagesz=1024m hugepages=2
>pci=pcie_bus_perf"
>+# CONFIG_USE_BOOTCOMMAND is not set
>+CONFIG_MISC_INIT_R=y
>+CONFIG_BOARD_EARLY_INIT_R=y
>+CONFIG_CMD_GREPENV=y
>+CONFIG_CMD_EEPROM=y
>+CONFIG_CMD_DM=y
>+CONFIG_CMD_GPT=y
>+CONFIG_CMD_GPIO=y
>+CONFIG_CMD_I2C=y
>+CONFIG_CMD_MMC=y
>+CONFIG_CMD_PCI=y
>+CONFIG_CMD_SF=y
>+CONFIG_CMD_USB=y
>+CONFIG_CMD_WDT=y
>+CONFIG_CMD_CACHE=y
>+CONFIG_MP=y
>+CONFIG_OF_CONTROL=y
>+CONFIG_OF_BOARD_FIXUP=y
>+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
>+CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-
>20-x"
>+CONFIG_MULTI_DTB_FIT=y
>+CONFIG_ENV_OVERWRITE=y
>+CONFIG_ENV_IS_IN_MMC=y
>+CONFIG_ENV_IS_IN_SPI_FLASH=y
>+CONFIG_ENV_ADDR=0x20500000
>+CONFIG_NET_RANDOM_ETHADDR=y
>+CONFIG_DM=y
>+CONFIG_SATA_CEVA=y
>+CONFIG_FSL_CAAM=y
>+CONFIG_DM_MMC=y
>+CONFIG_FSL_ESDHC=y
>+CONFIG_MTD=y
>+CONFIG_DM_SPI_FLASH=y
>+CONFIG_SPI_FLASH_EON=y
>+CONFIG_SPI_FLASH_SST=y
>+CONFIG_SPI_FLASH=y
>+CONFIG_SPI_FLASH_STMICRO=y
>+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
>+CONFIG_PHYLIB=y
>+CONFIG_PHY_AQUANTIA=y
>+CONFIG_PHY_CORTINA=y
>+CONFIG_PHY_REALTEK=y
>+CONFIG_PHY_VITESSE=y
>+CONFIG_DM_ETH=y
>+CONFIG_DM_MDIO=y
>+CONFIG_DM_MDIO_MUX=y
>+CONFIG_E1000=y
>+CONFIG_MDIO_MUX_I2CREG=y
>+CONFIG_FSL_LS_MDIO=y
>+CONFIG_PCI=y
>+CONFIG_DM_PCI=y
>+CONFIG_DM_PCI_COMPAT=y
>+CONFIG_PCIE_LAYERSCAPE_RC=y
>+CONFIG_DM_SCSI=y
>+CONFIG_DM_SERIAL=y
>+CONFIG_SPI=y
>+CONFIG_DM_SPI=y
>+CONFIG_FSL_DSPI=y
>+CONFIG_NXP_FSPI=y
>+CONFIG_USB=y
>+CONFIG_DM_USB=y
>+CONFIG_USB_XHCI_HCD=y
>+CONFIG_USB_XHCI_DWC3=y
>+CONFIG_WDT=y
>+CONFIG_WDT_SBSA=y
>+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
>+CONFIG_GIC_V3_ITS=y
>+CONFIG_DM_I2C=y
>+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
>+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
>+CONFIG_DM_RTC=y
>+CONFIG_DM_GPIO=y
>+CONFIG_CMD_DATE=y
>+CONFIG_RTC_PCF2127=y
>+CONFIG_I2C_MUX=y
>+CONFIG_I2C_MUX_PCA954x=y
>diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig
>b/configs/lx2162aqds_tfa_verified_boot_defconfig
>new file mode 100644
>index 0000000..7d0dbcd
>--- /dev/null
>+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
>@@ -0,0 +1,102 @@
>+CONFIG_ARM=y
>+CONFIG_TARGET_LX2162AQDS=y
>+CONFIG_SYS_TEXT_BASE=0x82000000
>+CONFIG_SYS_MALLOC_F_LEN=0x6000
>+CONFIG_ENV_SIZE=0x2000
>+CONFIG_ENV_SECT_SIZE=0x20000
>+CONFIG_ENV_OFFSET=0x500000
>+CONFIG_FSPI_AHB_EN_4BYTE=y
>+CONFIG_TFABOOT=y
>+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
>+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
>+CONFIG_AHCI=y
>+CONFIG_NR_DRAM_BANKS=3
>+CONFIG_FIT_VERBOSE=y
>+CONFIG_FIT_SIGNATURE=y
>+CONFIG_RSA=y
>+CONFIG_OF_BOARD_SETUP=y
>+CONFIG_OF_STDOUT_VIA_ALIAS=y
>+CONFIG_BOOTDELAY=10
>+CONFIG_USE_BOOTARGS=y
>+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0
>earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000
>default_hugepagesz=1024m hugepagesz=1024m hugepages=2
>pci=pcie_bus_perf"
>+# CONFIG_USE_BOOTCOMMAND is not set
>+CONFIG_MISC_INIT_R=y
>+CONFIG_BOARD_EARLY_INIT_R=y
>+CONFIG_CMD_GREPENV=y
>+CONFIG_CMD_EEPROM=y
>+CONFIG_CMD_DM=y
>+CONFIG_CMD_GPT=y
>+CONFIG_CMD_GPIO=y
>+CONFIG_CMD_I2C=y
>+CONFIG_CMD_MMC=y
>+CONFIG_CMD_PCI=y
>+CONFIG_CMD_SF=y
>+CONFIG_CMD_USB=y
>+CONFIG_CMD_WDT=y
>+CONFIG_CMD_CACHE=y
>+CONFIG_MP=y
>+CONFIG_OF_CONTROL=y
>+CONFIG_OF_BOARD_FIXUP=y
>+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds"
>+CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-
>20-x"
>+CONFIG_MULTI_DTB_FIT=y
>+CONFIG_ENV_OVERWRITE=y
>+CONFIG_ENV_IS_IN_MMC=y
>+CONFIG_ENV_IS_IN_SPI_FLASH=y
>+CONFIG_ENV_ADDR=0x20500000
>+CONFIG_NET_RANDOM_ETHADDR=y
>+CONFIG_DM=y
>+CONFIG_SATA_CEVA=y
>+CONFIG_FSL_CAAM=y
>+CONFIG_DM_MMC=y
>+CONFIG_FSL_ESDHC=y
>+CONFIG_MTD=y
>+CONFIG_DM_SPI_FLASH=y
>+CONFIG_SPI_FLASH_EON=y
>+CONFIG_SPI_FLASH_SST=y
>+CONFIG_SPI_FLASH=y
>+CONFIG_SPI_FLASH_STMICRO=y
>+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
>+CONFIG_PHYLIB=y
>+CONFIG_PHY_AQUANTIA=y
>+CONFIG_PHY_CORTINA=y
>+CONFIG_PHY_REALTEK=y
>+CONFIG_PHY_VITESSE=y
>+CONFIG_DM_ETH=y
>+CONFIG_DM_MDIO=y
>+CONFIG_DM_MDIO_MUX=y
>+CONFIG_E1000=y
>+CONFIG_MDIO_MUX_I2CREG=y
>+CONFIG_FSL_LS_MDIO=y
>+CONFIG_PCI=y
>+CONFIG_DM_PCI=y
>+CONFIG_DM_PCI_COMPAT=y
>+CONFIG_PCIE_LAYERSCAPE_RC=y
>+CONFIG_DM_SCSI=y
>+CONFIG_DM_SERIAL=y
>+CONFIG_SPI=y
>+CONFIG_DM_SPI=y
>+CONFIG_FSL_DSPI=y
>+CONFIG_NXP_FSPI=y
>+CONFIG_USB=y
>+CONFIG_DM_USB=y
>+CONFIG_USB_XHCI_HCD=y
>+CONFIG_USB_XHCI_DWC3=y
>+CONFIG_WDT=y
>+CONFIG_WDT_SBSA=y
>+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
>+CONFIG_GIC_V3_ITS=y
>+CONFIG_DM_I2C=y
>+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
>+CONFIG_I2C_DEFAULT_BUS_NUMBER=0
>+CONFIG_DM_RTC=y
>+CONFIG_DM_GPIO=y
>+CONFIG_CMD_DATE=y
>+CONFIG_RTC_PCF2127=y
>+CONFIG_I2C_MUX=y
>+CONFIG_I2C_MUX_PCA954x=y
>+CONFIG_TEE=y
>+CONFIG_OPTEE=y
>+CONFIG_CMD_OPTEE_RPMB=y
>+CONFIG_OPTEE_TA_AVB=y
>+CONFIG_SUPPORT_EMMC_RPMB=y
>diff --git a/include/configs/lx2160a_common.h
>b/include/configs/lx2160a_common.h
>index 0017ac5..837760f 100644
>--- a/include/configs/lx2160a_common.h
>+++ b/include/configs/lx2160a_common.h
>@@ -149,8 +149,10 @@
> /* USB */
> #ifdef CONFIG_USB
> #define CONFIG_HAS_FSL_XHCI_USB
>+#ifndef CONFIG_TARGET_LX2162AQDS
> #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> #endif
>+#endif
>
> /* FlexSPI */
> #ifdef CONFIG_NXP_FSPI
>diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
>new file mode 100644
>index 0000000..cb26956
>--- /dev/null
>+++ b/include/configs/lx2162aqds.h
>@@ -0,0 +1,169 @@
>+/* SPDX-License-Identifier: GPL-2.0+ */
>+/*
>+ * Copyright 2020 NXP
>+ */
>+
>+#ifndef __LX2162_QDS_H
>+#define __LX2162_QDS_H
>+
>+#include "lx2160a_common.h"
>+
>+/* USB */
>+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
>+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
>+
>+/*
>+ * Need to override existing (lx2160a) with lx2162aqds so set_board_info will
>+ * use proper prefix when creating full board_name (SYS_BOARD + type)
>+ */
>+#undef CONFIG_SYS_BOARD
>+#define CONFIG_SYS_BOARD "lx2162aqds"
>+
>+#undef CONFIG_SYS_NXP_SRDS_3
>+
>+/* Qixis */
>+#define QIXIS_XMAP_MASK 0x07
>+#define QIXIS_XMAP_SHIFT 5
>+#define QIXIS_RST_CTL_RESET_EN 0x30
>+#define QIXIS_LBMAP_DFLTBANK 0x00
>+#define QIXIS_LBMAP_ALTBANK 0x20
>+#define QIXIS_LBMAP_QSPI 0x00
>+#define QIXIS_RCW_SRC_QSPI 0xff
>+#define QIXIS_RST_CTL_RESET 0x31
>+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
>+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
>+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
>+#define QIXIS_LBMAP_MASK 0x0f
>+#define QIXIS_LBMAP_SD
>+#define QIXIS_LBMAP_EMMC
>+#define QIXIS_RCW_SRC_SD 0x08
>+#define QIXIS_RCW_SRC_EMMC 0x09
>+#define NON_EXTENDED_DUTCFG
>+#define QIXIS_SDID_MASK 0x07
>+#define QIXIS_ESDHC_NO_ADAPTER 0x7
>+
>+/* SYSCLK */
>+#define QIXIS_SYSCLK_100 0x0
>+#define QIXIS_SYSCLK_125 0x1
>+#define QIXIS_SYSCLK_133 0x2
>+
>+/* DDRCLK */
>+#define QIXIS_DDRCLK_100 0x0
>+#define QIXIS_DDRCLK_125 0x1
>+#define QIXIS_DDRCLK_133 0x2
>+
>+#define BRDCFG4_EMI1SEL_MASK 0xF8
>+#define BRDCFG4_EMI1SEL_SHIFT 3
>+#define BRDCFG4_EMI2SEL_MASK 0x07
>+#define BRDCFG4_EMI2SEL_SHIFT 0
>+
>+/* VID */
>+
>+#define I2C_MUX_CH_VOL_MONITOR 0xA
>+/* Voltage monitor on channel 2*/
>+#define I2C_VOL_MONITOR_ADDR 0x63
>+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
>+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
>+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
>+#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv"
>+#define CONFIG_VID
>+
>+/* The lowest and highest voltage allowed*/
>+#define VDD_MV_MIN 775
>+#define VDD_MV_MAX 925
>+
>+/* PM Bus commands code for LTC3882*/
>+#define PMBUS_CMD_PAGE 0x0
>+#define PMBUS_CMD_READ_VOUT 0x8B
>+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
>+#define PMBUS_CMD_VOUT_COMMAND 0x21
>+#define PWM_CHANNEL0 0x0
>+
>+#define CONFIG_VOL_MONITOR_LTC3882_SET
>+#define CONFIG_VOL_MONITOR_LTC3882_READ
>+
>+/* RTC */
>+#define CONFIG_SYS_RTC_BUS_NUM 0
>+#define I2C_MUX_CH_RTC 0xB
>+
>+/*
>+ * MMC
>+ */
>+#ifdef CONFIG_MMC
>+#ifndef __ASSEMBLY__
>+u8 qixis_esdhc_detect_quirk(void);
>+#endif
>+#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
>+#endif
>+
>+/* MAC/PHY configuration */
>+#if defined(CONFIG_FSL_MC_ENET)
>+#define CONFIG_MII
>+#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
>+
>+#define AQ_PHY_ADDR1 0x00
>+#define AQ_PHY_ADDR2 0x01
>+#define AQ_PHY_ADDR3 0x02
>+#define AQ_PHY_ADDR4 0x03
>+
>+#define CORTINA_NO_FW_UPLOAD
>+#define CORTINA_PHY_ADDR1 0x0
>+
>+#define INPHI_PHY_ADDR1 0x0
>+#define INPHI_PHY_ADDR2 0x1
>+#ifdef CONFIG_SD_BOOT
>+#define IN112525_FW_ADDR 0x980000
>+#else
>+#define IN112525_FW_ADDR 0x20980000
>+#endif
>+#define IN112525_FW_LENGTH 0x40000
>+
>+#define RGMII_PHY_ADDR1 0x01
>+#define RGMII_PHY_ADDR2 0x02
>+
>+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
>+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
>+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
>+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
>+
>+#endif
>+
>+/* EEPROM */
>+#define CONFIG_ID_EEPROM
>+#define CONFIG_SYS_I2C_EEPROM_NXID
>+#define CONFIG_SYS_EEPROM_BUS_NUM 0
>+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
>+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
>+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
>+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
>+
>+/* Initial environment variables */
>+#define CONFIG_EXTRA_ENV_SETTINGS \
>+ EXTRA_ENV_SETTINGS \
>+ "boot_scripts=lx2162aqds_boot.scr\0" \
>+ "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \
>+ "BOARD=lx2162aqds\0" \
>+ "xspi_bootcmd=echo Trying load from flexspi..;" \
>+ "sf probe 0:0 && sf read $load_addr " \
>+ "$kernel_start $kernel_size ; env exists secureboot &&"
> \
>+ "sf read $kernelheader_addr_r $kernelheader_start " \
>+ "$kernelheader_size && esbc_validate
>${kernelheader_addr_r}; "\
>+ " bootm $load_addr#$BOARD\0" \
>+ "sd_bootcmd=echo Trying load from sd card..;" \
>+ "mmc dev 0; mmcinfo; mmc read $load_addr "
> \
>+ "$kernel_addr_sd $kernel_size_sd ;" \
>+ "env exists secureboot && mmc read $kernelheader_addr_r
>"\
>+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
>+ " && esbc_validate ${kernelheader_addr_r};" \
>+ "bootm $load_addr#$BOARD\0" \
>+ "emmc_bootcmd=echo Trying load from emmc card..;" \
>+ "mmc dev 1; mmcinfo; mmc read $load_addr " \
>+ "$kernel_addr_sd $kernel_size_sd ;" \
>+ "env exists secureboot && mmc read $kernelheader_addr_r
>"\
>+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
>+ " && esbc_validate ${kernelheader_addr_r};" \
>+ "bootm $load_addr#$BOARD\0"
>+
>+#include <asm/fsl_secure_boot.h>
>+
>+#endif /* __LX2162_QDS_H */
>--
>2.7.4
Priyanka
