This minimal driver is only used to bind child devices.
Signed-off-by: Dario Binacchi <dario...@libero.it>
---
(no changes since v1)
doc/device-tree-bindings/arm/omap,prcm.txt | 63 ++++++++++++++++++++++
drivers/clk/ti/Makefile | 2 +-
drivers/clk/ti/omap4-cm.c | 22 ++++++++
3 files changed, 86 insertions(+), 1 deletion(-)
create mode 100644 doc/device-tree-bindings/arm/omap,prcm.txt
create mode 100644 drivers/clk/ti/omap4-cm.c
diff --git a/doc/device-tree-bindings/arm/omap,prcm.txt
b/doc/device-tree-bindings/arm/omap,prcm.txt
new file mode 100644
index 0000000000..123b17bd84
--- /dev/null
+++ b/doc/device-tree-bindings/arm/omap,prcm.txt
@@ -0,0 +1,63 @@
+OMAP PRCM bindings
+
+Power Reset and Clock Manager lists the device clocks and clockdomains under
+a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
+each describing one module and the clock hierarchy under it. see [1] for
+documentation about the individual clock/clockdomain nodes.
+
+[1] doc/device-tree-bindings/clock/ti,*.txt
+
+Required properties:
+- compatible: Must be one of:
+ "ti,am3-prcm"
+ "ti,am4-prcm"
+ "ti,omap2-prcm"
+ "ti,omap3-prm"
+ "ti,omap3-cm"
+ "ti,omap4-cm1"
+ "ti,omap4-prm"
+ "ti,omap4-cm2"
+ "ti,omap4-scrm"
+ "ti,omap5-prm"
+ "ti,omap5-cm-core-aon"
+ "ti,omap5-scrm"
+ "ti,omap5-cm-core"
+ "ti,dra7-prm"
+ "ti,dra7-cm-core-aon"
+ "ti,dra7-cm-core"
+ "ti,dm814-prcm"
+ "ti,dm816-prcm"
+- reg: Contains PRCM module register address range
+ (base address and length)
+- clocks: clocks for this module
+- clockdomains: clockdomains for this module
+
+Example:
+
+cm: cm@48004000 {
+ compatible = "ti,omap3-cm";
+ reg = <0x48004000 0x4000>;
+
+ cm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_clockdomains: clockdomains {
+ };
+}
+
+&cm_clocks {
+ omap2_32k_fck: omap_32k_fck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+};
+
+&cm_clockdomains {
+ core_l3_clkdm: core_l3_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&sdrc_ick>;
+ };
+};
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a279a2838d..0b7e61cdf7 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,7 @@
# Copyright (C) 2020 Dario Binacchi <dario...@libero.it>
#
-obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o omap4-cm.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
diff --git a/drivers/clk/ti/omap4-cm.c b/drivers/clk/ti/omap4-cm.c
new file mode 100644
index 0000000000..3cdc9b2888
--- /dev/null
+++ b/drivers/clk/ti/omap4-cm.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP4 clock manager (cm)
+ *
+ * Copyright (C) 2020 Dario Binacchi <dario...@libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+
+static const struct udevice_id ti_omap4_cm_ids[] = {
+ {.compatible = "ti,omap4-cm"},
+ {}
+};
+
+U_BOOT_DRIVER(ti_omap4_cm) = {
+ .name = "ti_omap4_cm",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = ti_omap4_cm_ids,
+ .bind = dm_scan_fdt_dev,
+};
--
2.17.1
