On 09.09.20 01:32, Chris Packham wrote:
On 7/09/20 3:05 pm, Pratyush Yadav wrote:
On 06/09/20 08:34PM, Chris Packham wrote:
On 5/09/20 3:39 am, Pratyush Yadav wrote:
Chris,
On 04/09/20 09:04PM, Pratyush Yadav wrote:
The SPI NOR core will get Octal DTR in following commits. This has
presented a significant challenge of keeping the SPL size in check on
the x530 platform.
On a previous iteration of the series, adding a set of compile-time
switches got the build working. But rebasing on the latest master breaks
the build again. We are fighting a losing battle here. Every addition to
either the SPI NOR core in the future, or any other core part of U-Boot
will potentially lead to the SPL size going beyond the limit and the
build failing.
To combat this we will have to keep adding more and more compile-time
switches, increasing the complexity of the code in the process. This is
not sustainable. So use tiny SPI NOR instead. It is designed with
size-limited SPL binaries in mind, and will afford us more breathing
room.
To enable tiny SPI NOR, CONFIG_SPI_FLASH_BAR has to be disabled.
Signed-off-by: Pratyush Yadav <p.ya...@ti.com>
---
configs/x530_defconfig | 1 -
1 file changed, 1 deletion(-)
Can you please test these changes on your board and confirm that tiny
SPI NOR works for you?
I'll take a look when I get a chance. I'm not actually sure what the
true SPL size limit is for Armada-385. It's possible we could avoid the
build issues simply by bumping the limit up.
Bumping the limit up would be the best solution. Please check if we can
do that.
I've reached out to Marvell to see if they can tell me what the actual
size limit is.
Stefan, do you happen to know? The Armada-XP talks about using the L2
cache as SRAM but it's not immediately clear if that's whats going on
with the Armada-385.
Sorry, I can't answer this question without looking deeper into it.
Right now, my time is very limited though. Sorry.
Thanks,
Stefan
