On Fri, Oct 2, 2020 at 7:40 AM Simon Glass <s...@chromium.org> wrote: > > Hi Heiko, > > On Thu, 1 Oct 2020 at 12:40, Heiko Stuebner <he...@sntech.de> wrote: > > > > From: Heiko Stuebner <heiko.stueb...@theobroma-systems.com> > > > > The SRAM on the PX30 is not big enough to hold multiple DDR configs > > so it needs to be selected during build. > > > > So far simply the DDR3 config was always selected and getting DDR4 > > or LPDDR2/3 initialized would require a code modification. > > > > So add Kconfig options similar to RK3399 to allow selecting the DDR4 > > and LPDDR2/3 options instead, while DDR3 stays the default as before. > > > > Signed-off-by: Heiko Stuebner <heiko.stueb...@theobroma-systems.com> > > --- > > drivers/ram/rockchip/Kconfig | 21 +++++++++++++++++++++ > > drivers/ram/rockchip/sdram_px30.c | 8 ++++++++ > > 2 files changed, 29 insertions(+) > > > > diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig > > index 8e97c2f49e..c459bbf5e2 100644 > > --- a/drivers/ram/rockchip/Kconfig > > +++ b/drivers/ram/rockchip/Kconfig > > @@ -22,6 +22,27 @@ config RAM_ROCKCHIP_DEBUG > > This is an option for developers to understand the ram drivers > > initialization, configurations and etc. > > > > +config RAM_PX30_DDR4 > > + bool "DDR3 support for Rockchip PX30" > > + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 > > + help > > + This enables DDR4 sdram support instead of the default DDR3 > > support > > + on Rockchip PC30 SoCs. > > + > > +config RAM_PX30_LPDDR2 > > + bool "LPDDR2 support for Rockchip PX30" > > + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 > > + help > > + This enables LPDDR2 sdram support instead of the default DDR3 > > support > > + on Rockchip PC30 SoCs. > > + > > +config RAM_PX30_LPDDR3 > > + bool "LPDDR3 support for Rockchip PX30" > > + depends on RAM_ROCKCHIP && ROCKCHIP_PX30 > > + help > > + This enables LPDDR3 sdram support instead of the default DDR3 > > support > > + on Rockchip PC30 SoCs. > > + > > config RAM_RK3399_LPDDR4 > > bool "LPDDR4 support for Rockchip RK3399" > > depends on RAM_ROCKCHIP && ROCKCHIP_RK3399 > > diff --git a/drivers/ram/rockchip/sdram_px30.c > > b/drivers/ram/rockchip/sdram_px30.c > > index fd5763d0a0..2f1f6e9c0c 100644 > > --- a/drivers/ram/rockchip/sdram_px30.c > > +++ b/drivers/ram/rockchip/sdram_px30.c > > @@ -125,7 +125,15 @@ u32 addrmap[][8] = { > > struct dram_info dram_info; > > > > struct px30_sdram_params sdram_configs[] = { > > +#if defined(CONFIG_RAM_PX30_DDR4) > > +#include "sdram-px30-ddr4-detect-333.inc" > > +#elif defined(CONFIG_RAM_PX30_LPDDR2) > > +#include "sdram-px30-lpddr2-detect-333.inc" > > +#elif defined(CONFIG_RAM_PX30_LPDDR3) > > +#include "sdram-px30-lpddr3-detect-333.inc" > > +#else > > #include "sdram-px30-ddr3-detect-333.inc" > > +#endif > > How about putting this in the device tree? I think that would be a better > place.
I did try this while support Engicam PX30.Core. Seems impossible to drive with the timings via device tree. With PLATDATA and disabled unused drivers in TPL, I still way behind 0x3000 bytes. MKIMAGE u-boot.itb MKIMAGE tpl/u-boot-tpl-rockchip.bin Error: SPL image is too large (size 0x5800 than 0x2800) Error: Bad parameters for image type Jagan.