> From: Stefan Roese <s...@denx.de> > Date: Fri, 16 Oct 2020 15:08:46 +0200 > > Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. > Here the only 2 instructions are allowed in the first few bytes of the > image. And these instructions need to be one branch and a nop. This > patch adds the necessary nop after the nop, to that the common MIPS > image is compatible with this Octeon header. > > The tool to patch the Octeon boot header into the image will be send in > a follow-up patch.
Since the moved instruction is no longer in a delay slot, you should probably remove the extra space before the instruction. Cheers, Mark > Signed-off-by: Stefan Roese <s...@denx.de> > Cc: Aaron Williams <awilli...@marvell.com> > Cc: Chandrakala Chavva <ccha...@marvell.com> > Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com> > --- > arch/mips/cpu/start.S | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S > index d0c412236d..6de2470cc2 100644 > --- a/arch/mips/cpu/start.S > +++ b/arch/mips/cpu/start.S > @@ -75,8 +75,13 @@ > > ENTRY(_start) > /* U-Boot entry point */ > + /* > + * Octeon needs special handling here, as the binary might be > + * patched to add a boot header for SPI, NAND or MMC booting. Only > + * one branch plus nop is allowed here. > + */ > b reset > - mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing > + nop > > #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) > /* > @@ -123,6 +128,7 @@ ENTRY(_start) > #endif > > reset: > + mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing > #if __mips_isa_rev >= 6 > mfc0 t0, CP0_CONFIG, 5 > and t0, t0, MIPS_CONF5_VP > -- > 2.28.0 > >
