Hi Meenakshi,
> -----Original Message-----
> From: U-Boot <u-boot-boun...@lists.denx.de> On Behalf Of
> meenakshi.aggar...@nxp.com
> Sent: Monday, September 7, 2020 6:12 PM
> To: u-boot@lists.denx.de; Priyanka Jain <priyanka.j...@nxp.com>
> Cc: Varun Sethi <v.se...@nxp.com>; Meenakshi Aggarwal
> <meenakshi.aggar...@nxp.com>
> Subject: [PATCH v3 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
>
> From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
>
> LX2162 is LX2160 based SoC, it has same die as of LX2160
> with different packaging.
>
> LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
> microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
> sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
> interface to support three PCIe gen3 interface.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> ---
> arch/arm/cpu/armv8/Kconfig | 2 +-
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +++++++++++++--
> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++--
> arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58
> ++++++++++++++++++++++
> .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 8 +--
> arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++++++-
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 10 ++--
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +--
> arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +-
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++---
> arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 ++-
> .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 ++--
> drivers/ddr/fsl/Kconfig | 1 +
> drivers/net/fsl-mc/Kconfig | 4 +-
> drivers/net/ldpaa_eth/Makefile | 1 +
> drivers/pci/Kconfig | 4 +-
> drivers/pci/pcie_layerscape_ep.c | 4 +-
> drivers/pci/pcie_layerscape_fixup_common.c | 7 ++-
> 19 files changed, 170 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> index 3655990..f247441 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -115,7 +115,7 @@ config PSCI_RESET
> !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
> !TARGET_LS1046AFRWY && \
> !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
> - !TARGET_LX2160AQDS && \
> + !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
> !ARCH_UNIPHIER && !TARGET_S32V234EVB
> help
> Most armv8 systems have PSCI support enabled in EL3, either through
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index be51b7d..4d46587 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -208,6 +208,35 @@ config ARCH_LS2080A
> imply DISTRO_DEFAULTS
> imply PANIC_HANG
>
> +config ARCH_LX2162A
> + bool
> + select ARMV8_SET_SMPEN
> + select FSL_LSCH3
> + select NXP_LSCH3_2
> + select SYS_HAS_SERDES
> + select SYS_FSL_SRDS_1
> + select SYS_FSL_SRDS_2
> + select SYS_FSL_DDR
> + select SYS_FSL_DDR_LE
> + select SYS_FSL_DDR_VER_50
> + select SYS_FSL_EC1
> + select SYS_FSL_EC2
> + select SYS_FSL_ERRATUM_A050106
> + select SYS_FSL_HAS_RGMII
> + select SYS_FSL_HAS_SEC
> + select SYS_FSL_HAS_CCN508
> + select SYS_FSL_HAS_DDR4
> + select SYS_FSL_SEC_COMPAT_5
> + select SYS_FSL_SEC_LE
> + select ARCH_EARLY_INIT_R
> + select BOARD_EARLY_INIT_F
> + select SYS_I2C_MXC
> + select RESV_RAM if GIC_V3_ITS
> + imply DISTRO_DEFAULTS
> + imply PANIC_HANG
> + imply SCSI
> + imply SCSI_AHCI
> +
> config ARCH_LX2160A
> bool
> select ARMV8_SET_SMPEN
> @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
> help
> USB3.0 Receiver needs to enable fixed equalization
> for each of PHY instances in an SOC. This is similar
> - to erratum A-009007, but this one is for LX2160A,
> + to erratum A-009007, but this one is for LX2160A and LX2162A,
> and the register value is different.
>
> config SYS_FSL_ERRATUM_A010315
> @@ -362,6 +391,7 @@ config MAX_CPUS
> default 16 if ARCH_LS2080A
> default 8 if ARCH_LS1088A
> default 16 if ARCH_LX2160A
> + default 16 if ARCH_LX2162A
> default 1
> help
> Set this number to the maximum number of possible CPUs in the SoC.
> @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
> int "DUART clock divider"
> default 1 if ARCH_LS1043A
> default 4 if ARCH_LX2160A
> + default 4 if ARCH_LX2162A
> default 2
> help
> This is the divider that is used to derive DUART clock from Platform
> @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
> default 4 if ARCH_LS1012A
> default 4 if ARCH_LS1028A
> default 8 if ARCH_LX2160A
> + default 8 if ARCH_LX2162A
> default 8 if ARCH_LS1088A
> default 2
> help
> @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
> default 4 if ARCH_LS1012A
> default 4 if ARCH_LS1028A
> default 8 if ARCH_LX2160A
> + default 8 if ARCH_LX2162A
> default 8 if ARCH_LS1088A
> default 2
> help
> @@ -560,14 +593,14 @@ config SYS_FSL_EC1
> bool
> help
> Ethernet controller 1, this is connected to
> - MAC17 for LX2160A or to MAC3 for other SoCs
> + MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
> Provides DPAA2 capabilities
>
> config SYS_FSL_EC2
> bool
> help
> Ethernet controller 2, this is connected to
> - MAC18 for LX2160A or to MAC4 for other SoCs
> + MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
> Provides DPAA2 capabilities
>
> config SYS_FSL_ERRATUM_A008336
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index 9ecb372..598c36e 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
> obj-y += icid.o lx2160_ids.o
> endif
>
> +ifneq ($(CONFIG_ARCH_LX2162A),)
> +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
> +obj-y += icid.o lx2160_ids.o
> +endif
> +
> ifneq ($(CONFIG_ARCH_LS2080A),)
> obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
> obj-y += icid.o ls2088_ids.o
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 8a2f404..59d5265 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2017-2019 NXP
> + * Copyright 2017-2020 NXP
> * Copyright 2014-2015 Freescale Semiconductor, Inc.
> */
>
> @@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
> CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
> CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
> CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
> + CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
> + CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
> + CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
> };
>
> #define EARLY_PGTABLE_SIZE 0x5000
> @@ -403,7 +406,7 @@ void cpu_name(char *name)
> for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
> if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
> strcpy(name, cpu_type_list[i].name);
> -#ifdef CONFIG_ARCH_LX2160A
> +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Please make sure such change is made in all files. The below one is missed.
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> if (IS_C_PROCESSOR(svr))
> strcat(name, "C");
> #endif
[...]
