RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.
RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.
Signed-off-by: Biju Das <biju.das...@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
---
v5->v6
* Optimized the unique CPU identification method by using Renesas SoC
identification driver.
v4->v5
* Add support for unique identification of RZ/G2 CPU types
(Ref:
https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das...@bp.renesas.com/)
v3->v4
* Dropped CPU info reporting logic for RZ/G2. Will address this later.
* Added PRRID's for RZG2[HMNE]
(Ref:
https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das...@bp.renesas.com/)
v2->v3
* Reworked as per Marek's suggestion
* Added rzg2_get_cpu_type function to get cpu_type by matching TFA
compatible string
* Removed SoC family type Enum
(Ref:
https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das...@bp.renesas.com/)
v1->v2:
* Add comment's related to loop logic
(ref:
https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das...@bp.renesas.com/)
v1:
* New patch
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das...@bp.renesas.com/
---
arch/arm/mach-rmobile/cpu_info-rcar.c | 22 ++++++-
arch/arm/mach-rmobile/cpu_info.c | 10 +++-
arch/arm/mach-rmobile/include/mach/rmobile.h | 60 +++++++++++++++-----
3 files changed, 73 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..08345503a2 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
#include <asm/io.h>
+#include <soc.h>
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
@@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
#endif
}
+static bool is_rzg_family(void)
+{
+ bool rzg_family_type = false;
+ struct udevice *soc;
+ char name[16];
+
+ if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
+ if (!strcmp(name, "RZ/G2"))
+ rzg_family_type = true;
+ }
+
+ return rzg_family_type;
+}
+
u32 rmobile_get_cpu_type(void)
{
- return (rmobile_get_prr() & 0x00007F00) >> 8;
+ u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
+
+ if (is_rzg_family())
+ soc_id |= RZG_CPU_MASK;
+
+ return soc_id;
}
u32 rmobile_get_cpu_rev_integer(void)
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..b19b7e3044 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,12 +3,12 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu...@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
-#include <cpu_func.h>
#include <asm/cache.h>
-#include <init.h>
#include <asm/io.h>
+#include <common.h>
+#include <cpu_func.h>
#include <env.h>
+#include <init.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
@@ -59,6 +59,10 @@ static const struct {
} rmobile_cpuinfo[] = {
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
+ { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
+ { RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
+ { RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
+ { RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..da099fa4c3 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -24,21 +24,51 @@
#endif
#endif /* CONFIG_ARCH_RMOBILE */
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_SH73A0 0x37
-#define RMOBILE_CPU_TYPE_R8A7740 0x40
-#define RMOBILE_CPU_TYPE_R8A7790 0x45
-#define RMOBILE_CPU_TYPE_R8A7791 0x47
-#define RMOBILE_CPU_TYPE_R8A7792 0x4A
-#define RMOBILE_CPU_TYPE_R8A7793 0x4B
-#define RMOBILE_CPU_TYPE_R8A7794 0x4C
-#define RMOBILE_CPU_TYPE_R8A7795 0x4F
-#define RMOBILE_CPU_TYPE_R8A7796 0x52
-#define RMOBILE_CPU_TYPE_R8A77965 0x55
-#define RMOBILE_CPU_TYPE_R8A77970 0x54
-#define RMOBILE_CPU_TYPE_R8A77980 0x56
-#define RMOBILE_CPU_TYPE_R8A77990 0x57
-#define RMOBILE_CPU_TYPE_R8A77995 0x58
+/* PRR IDs */
+#define SOC_ID_SH73A0 0x37
+#define SOC_ID_R8A7740 0x40
+#define SOC_ID_R8A774A1 0x52
+#define SOC_ID_R8A774B1 0x55
+#define SOC_ID_R8A774C0 0x57
+#define SOC_ID_R8A774E1 0x4F
+#define SOC_ID_R8A7790 0x45
+#define SOC_ID_R8A7791 0x47
+#define SOC_ID_R8A7792 0x4A
+#define SOC_ID_R8A7793 0x4B
+#define SOC_ID_R8A7794 0x4C
+#define SOC_ID_R8A7795 0x4F
+#define SOC_ID_R8A7796 0x52
+#define SOC_ID_R8A77965 0x55
+#define SOC_ID_R8A77970 0x54
+#define SOC_ID_R8A77980 0x56
+#define SOC_ID_R8A77990 0x57
+#define SOC_ID_R8A77995 0x58
+
+/* CPU IDs */
+#define RMOBILE_CPU_TYPE_SH73A0 SOC_ID_SH73A0
+#define RMOBILE_CPU_TYPE_R8A7740 SOC_ID_R8A7740
+#define RMOBILE_CPU_TYPE_R8A774A1 (SOC_ID_R8A774A1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774B1 (SOC_ID_R8A774B1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774C0 (SOC_ID_R8A774C0 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774E1 (SOC_ID_R8A774E1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A7790 SOC_ID_R8A7790
+#define RMOBILE_CPU_TYPE_R8A7791 SOC_ID_R8A7791
+#define RMOBILE_CPU_TYPE_R8A7792 SOC_ID_R8A7792
+#define RMOBILE_CPU_TYPE_R8A7793 SOC_ID_R8A7793
+#define RMOBILE_CPU_TYPE_R8A7794 SOC_ID_R8A7794
+#define RMOBILE_CPU_TYPE_R8A7795 SOC_ID_R8A7795
+#define RMOBILE_CPU_TYPE_R8A7796 SOC_ID_R8A7796
+#define RMOBILE_CPU_TYPE_R8A77965 SOC_ID_R8A77965
+#define RMOBILE_CPU_TYPE_R8A77970 SOC_ID_R8A77970
+#define RMOBILE_CPU_TYPE_R8A77980 SOC_ID_R8A77980
+#define RMOBILE_CPU_TYPE_R8A77990 SOC_ID_R8A77990
+#define RMOBILE_CPU_TYPE_R8A77995 SOC_ID_R8A77995
+
+/*
+ * R-Car and RZ/G SoC's share same PRR ID's for the same SoC type. The
+ * RZG_CPU_MASK is used to provide a unique CPU identification for RZ/G SoC's.
+ */
+#define RZG_CPU_MASK 0x1000
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
--
2.17.1
