Hi Daniel,
On 28.10.20 15:09, Stefan Roese wrote:
Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC.
Here the only 2 instructions are allowed in the first few bytes of the
image. And these instructions need to be one branch and a nop. This
patch adds the necessary nop after the nop, to that the common MIPS
image is compatible with this Octeon header.
The tool to patch the Octeon boot header into the image will be send in
a follow-up patch.
Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Aaron Williams <awilli...@marvell.com>
Cc: Chandrakala Chavva <ccha...@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
---
v2:
- Enhance comment
- Fix delay slot indentation
Do you have any comments on this patchset? What is your plan with it?
Could you integrate it in the upcoming release? It includes some fixes,
which would be really helpful in the release and does not touch
platforms other than Octeon (other than this small patch here).
Thanks,
Stefan
arch/mips/cpu/start.S | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d0c412236d..335aafa6a8 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -74,9 +74,14 @@
.endm
ENTRY(_start)
- /* U-Boot entry point */
+ /*
+ * U-Boot entry point.
+ * Do not add instructions to the branch delay slot! Some SoC's
+ * like Octeon might patch the final U-Boot binary at this location
+ * with additional boot headers.
+ */
b reset
- mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
+ nop
#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
/*
@@ -123,6 +128,7 @@ ENTRY(_start)
#endif
reset:
+ mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
#if __mips_isa_rev >= 6
mfc0 t0, CP0_CONFIG, 5
and t0, t0, MIPS_CONF5_VP
Viele Grüße,
Stefan
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Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
