From: Chee Hong Ang <chee.hong....@intel.com>
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang <chee.hong....@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin....@intel.com>
---
v2
---
Call secure register access helper function to write the secure register
---
drivers/mmc/socfpga_dw_mmc.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..04f67754f5 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <log.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/secure_reg_helper.h>
#include <asm/arch/system_manager.h>
#include <clk.h>
#include <dm.h>
@@ -13,6 +14,7 @@
#include <errno.h>
#include <fdtdec.h>
#include <dm/device_compat.h>
+#include <linux/intel-smc.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <malloc.h>
@@ -58,10 +60,16 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ socfpga_secure_reg_write32(sdmmc_mask,
+ SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC);
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.13.0
