Hi Simon, On Sat, Dec 19, 2020 at 7:58 AM Simon Glass <s...@chromium.org> wrote:
> Hi Padmarao, > > On Mon, 14 Dec 2020 at 04:09, Padmarao Begari > <padmarao.beg...@microchip.com> wrote: > > > > Add clock driver code for the Microchip PolarFire SoC. This driver > > handles reset and clock control of the Microchip PolarFire SoC device. > > > > Signed-off-by: Padmarao Begari <padmarao.beg...@microchip.com> > > Reviewed-by: Anup Patel <anup.pa...@wdc.com> > > --- > > drivers/clk/Kconfig | 1 + > > drivers/clk/Makefile | 1 + > > drivers/clk/microchip/Kconfig | 5 + > > drivers/clk/microchip/Makefile | 1 + > > drivers/clk/microchip/mpfs_clk.c | 127 +++++++++++++ > > drivers/clk/microchip/mpfs_clk.h | 19 ++ > > drivers/clk/microchip/mpfs_clk_cfg.c | 134 ++++++++++++++ > > drivers/clk/microchip/mpfs_clk_periph.c | 173 ++++++++++++++++++ > > .../dt-bindings/clock/microchip-mpfs-clock.h | 45 +++++ > > 9 files changed, 506 insertions(+) > > create mode 100644 drivers/clk/microchip/Kconfig > > create mode 100644 drivers/clk/microchip/Makefile > > create mode 100644 drivers/clk/microchip/mpfs_clk.c > > create mode 100644 drivers/clk/microchip/mpfs_clk.h > > create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c > > create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c > > create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h > > Rather than allocating memory in your driver should use driver model's > auto-alloc feature. > > ok > > > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > > index 4dfbad7986..1161fe7b5a 100644 > > --- a/drivers/clk/Kconfig > > +++ b/drivers/clk/Kconfig > > @@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig" > > source "drivers/clk/imx/Kconfig" > > source "drivers/clk/kendryte/Kconfig" > > source "drivers/clk/meson/Kconfig" > > +source "drivers/clk/microchip/Kconfig" > > source "drivers/clk/mvebu/Kconfig" > > source "drivers/clk/owl/Kconfig" > > source "drivers/clk/renesas/Kconfig" > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > > index d1e295ac7c..bd8a6eed88 100644 > > --- a/drivers/clk/Makefile > > +++ b/drivers/clk/Makefile > > @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ > > obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ > > obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o > > obj-$(CONFIG_CLK_K210) += kendryte/ > > +obj-$(CONFIG_CLK_MPFS) += microchip/ > > obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o > > obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o > > obj-$(CONFIG_CLK_OWL) += owl/ > > diff --git a/drivers/clk/microchip/Kconfig > b/drivers/clk/microchip/Kconfig > > new file mode 100644 > > index 0000000000..b70241559d > > --- /dev/null > > +++ b/drivers/clk/microchip/Kconfig > > @@ -0,0 +1,5 @@ > > +config CLK_MPFS > > + bool "Clock support for Microchip PolarFire SoC" > > + depends on CLK && CLK_CCF > > + help > > + This enables support clock driver for Microchip PolarFire SoC > platform. > > diff --git a/drivers/clk/microchip/Makefile > b/drivers/clk/microchip/Makefile > > new file mode 100644 > > index 0000000000..904b345d75 > > --- /dev/null > > +++ b/drivers/clk/microchip/Makefile > > @@ -0,0 +1 @@ > > +obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o > > diff --git a/drivers/clk/microchip/mpfs_clk.c > b/drivers/clk/microchip/mpfs_clk.c > > new file mode 100644 > > index 0000000000..1b1b66ef64 > > --- /dev/null > > +++ b/drivers/clk/microchip/mpfs_clk.c > > @@ -0,0 +1,127 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2020 Microchip Technology Inc. > > + * Padmarao Begari <padmarao.beg...@microchip.com> > > + */ > > +#include <common.h> > > +#include <clk.h> > > +#include <clk-uclass.h> > > +#include <dm.h> > > +#include <log.h> > > +#include <dm/device.h> > > +#include <dm/devres.h> > > +#include <dm/uclass.h> > > +#include <malloc.h> > > +#include <linux/err.h> > > + > > +#include "mpfs_clk.h" > > + > > +/* All methods are delegated to CCF clocks */ > > + > > +static ulong mpfs_clk_get_rate(struct clk *clk) > > +{ > > + struct clk *c; > > + int err = clk_get_by_id(clk->id, &c); > > + > > + if (err) > > + return err; > > + return clk_get_rate(c); > > +} > > + > > +static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate) > > +{ > > + struct clk *c; > > + int err = clk_get_by_id(clk->id, &c); > > + > > + if (err) > > + return err; > > + return clk_set_rate(c, rate); > > +} > > + > > +static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent) > > +{ > > + struct clk *c, *p; > > + int err = clk_get_by_id(clk->id, &c); > > + > > + if (err) > > + return err; > > + > > + err = clk_get_by_id(parent->id, &p); > > + if (err) > > + return err; > > + > > + return clk_set_parent(c, p); > > +} > > + > > +static int mpfs_clk_endisable(struct clk *clk, bool enable) > > +{ > > + struct clk *c; > > + int err = clk_get_by_id(clk->id, &c); > > + > > + if (err) > > + return err; > > + return enable ? clk_enable(c) : clk_disable(c); > > +} > > + > > +static int mpfs_clk_enable(struct clk *clk) > > +{ > > + return mpfs_clk_endisable(clk, true); > > +} > > + > > +static int mpfs_clk_disable(struct clk *clk) > > +{ > > + return mpfs_clk_endisable(clk, false); > > +} > > + > > +static int mpfs_clk_probe(struct udevice *dev) > > +{ > > + int ret; > > + void __iomem *base; > > + u32 clk_rate; > > + struct clk *clk; > > + const char *parent_clk_name; > > + > > + base = dev_read_addr_ptr(dev); > > + if (!base) > > + return -ENODEV; > > + > > + clk = kzalloc(sizeof(*clk), GFP_KERNEL); > > + if (!clk) > > + return -ENOMEM; > > + > > + ret = clk_get_by_index(dev, 0, clk); > > + if (ret) > > + return ret; > > + > > + dev_read_u32(clk->dev, "clock-frequency", &clk_rate); > > + parent_clk_name = clk->dev->name; > > + > > + ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name); > > + if (ret) > > + return ret; > > + > > + ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb"); > > + > > + return ret; > > +} > > + > > +static const struct clk_ops mpfs_clk_ops = { > > + .set_rate = mpfs_clk_set_rate, > > + .get_rate = mpfs_clk_get_rate, > > + .set_parent = mpfs_clk_set_parent, > > + .enable = mpfs_clk_enable, > > + .disable = mpfs_clk_disable, > > +}; > > + > > +static const struct udevice_id mpfs_of_match[] = { > > + { .compatible = "microchip,mpfs-clkcfg" }, > > + { } > > +}; > > + > > +U_BOOT_DRIVER(mpfs_clk) = { > > + .name = "mpfs_clk", > > + .id = UCLASS_CLK, > > + .of_match = mpfs_of_match, > > + .ops = &mpfs_clk_ops, > > + .probe = mpfs_clk_probe, > > +}; > > diff --git a/drivers/clk/microchip/mpfs_clk.h > b/drivers/clk/microchip/mpfs_clk.h > > new file mode 100644 > > index 0000000000..35eecc02c0 > > --- /dev/null > > +++ b/drivers/clk/microchip/mpfs_clk.h > > @@ -0,0 +1,19 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright (C) 2020 Microchip Technology Inc. > > + * Padmarao Begari <padmarao.beg...@microchip.com> > > + */ > > +#ifndef __MICROCHIP_MPFS_CLK_H > > +#define __MICROCHIP_MPFS_CLK_H > > + > > +#include <linux/clk-provider.h> > > + > > +int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate, > > + const char *parent_name); > > +int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate, > > + const char *parent_name); > > +int divider_get_val(unsigned long rate, unsigned long parent_rate, > > + const struct clk_div_table *table, > > + u8 width, unsigned long flags); > > Comments? > > ok > > + > > +#endif /* __MICROCHIP_MPFS_CLK_H */ > > diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c > b/drivers/clk/microchip/mpfs_clk_cfg.c > > new file mode 100644 > > index 0000000000..44db14c664 > > --- /dev/null > > +++ b/drivers/clk/microchip/mpfs_clk_cfg.c > > @@ -0,0 +1,134 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2020 Microchip Technology Inc. > > + * Padmarao Begari <padmarao.beg...@microchip.com> > > + */ > > +#include <common.h> > > +#include <clk.h> > > +#include <clk-uclass.h> > > +#include <dm/device.h> > > +#include <dm/devres.h> > > +#include <dm/uclass.h> > > +#include <asm/io.h> > > +#include <linux/err.h> > > +#include <dt-bindings/clock/microchip-mpfs-clock.h> > > Please check header order. > > ok https://www.denx.de/wiki/U-Boot/CodingStyle > > > + > > +#include "mpfs_clk.h" > > + > > +#define MPFS_CFG_CLOCK "mpfs_cfg_clock" > > + > > +#define REG_CLOCK_CONFIG_CR 0x08 > > + > > +static const struct clk_div_table mpfs_div_cpu_axi_table[] = { > > + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, > > + { 0, 0 } > > +}; > > + > > +static const struct clk_div_table mpfs_div_ahb_table[] = { > > + { 1, 2 }, { 2, 4}, { 3, 8 }, > > + { 0, 0 } > > +}; > > + > > +struct mpfs_cfg_clock { > > + unsigned int id; > > + const char *name; > > + u8 shift; > > + u8 width; > > + const struct clk_div_table *table; > > + unsigned long flags; > > +}; > > comments > > ok > > + > > +struct mpfs_cfg_hw_clock { > > + struct mpfs_cfg_clock cfg; > > + void __iomem *sys_base; > > + u32 prate; > > + struct clk hw; > > +}; > > comments!!! > > ok Regards Padmarao > > Regards, > Simon >