On 1/4/21 12:39 PM, Jernej Škrabec wrote: > Dne ponedeljek, 04. januar 2021 ob 03:39:52 CET je Samuel Holland napisal(a): >> On 1/3/21 3:26 AM, Jernej Skrabec wrote: >>> Allwinner H616 supports many types of DRAM. Most notably it supports >>> LPDDR4. However, all commercially available boards at this time use >>> only DDR3, so this commit adds only DDR3 support. >>> >>> Controller and MBUS are very similar to H6 but PHY is completely >>> unknown. >>> >>> Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net> >>> --- >>> >>> arch/arm/include/asm/arch-sunxi/dram.h | 2 + >>> .../include/asm/arch-sunxi/dram_sun50i_h616.h | 159 +++ >>> arch/arm/mach-sunxi/Kconfig | 43 + >>> arch/arm/mach-sunxi/Makefile | 2 + >>> arch/arm/mach-sunxi/dram_sun50i_h616.c | 1023 +++++++++++++++++ >>> arch/arm/mach-sunxi/dram_timings/Makefile | 2 + >>> .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 94 ++ >>> 7 files changed, 1325 insertions(+) >>> create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h >>> create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h616.c >>> create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c >>> >>> diff --git a/arch/arm/include/asm/arch-sunxi/dram.h >>> b/arch/arm/include/asm/arch-sunxi/dram.h index 8002b7efdc19..c3b3e1f512b2 >>> 100644 >>> --- a/arch/arm/include/asm/arch-sunxi/dram.h >>> +++ b/arch/arm/include/asm/arch-sunxi/dram.h >>> @@ -29,6 +29,8 @@ >>> >>> #include <asm/arch/dram_sun9i.h> >>> #elif defined(CONFIG_MACH_SUN50I_H6) >>> #include <asm/arch/dram_sun50i_h6.h> >>> >>> +#elif defined(CONFIG_MACH_SUN50I_H616) >>> +#include <asm/arch/dram_sun50i_h616.h> >>> >>> #else >>> #include <asm/arch/dram_sun4i.h> >>> #endif >>> >>> diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h >>> b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h new file mode 100644 >>> index 000000000000..5d105afd6110 >>> --- /dev/null >>> +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h >>> @@ -0,0 +1,159 @@ >>> +/* >>> + * H616 dram controller register and constant defines >>> + * >>> + * (C) Copyright 2020 Jernej Skrabec <jernej.skra...@siol.net> >>> + * >>> + * Based on H6 one, which is: >>> + * (C) Copyright 2017 Icenowy Zheng <icen...@aosc.io> >>> + * >>> + * SPDX-License-Identifier: GPL-2.0+ >>> + */ >>> + >>> +#ifndef _SUNXI_DRAM_SUN50I_H616_H >>> +#define _SUNXI_DRAM_SUN50I_H616_H >>> + >>> +#include <stdbool.h> >>> +#ifndef __ASSEMBLY__ >>> +#include <linux/bitops.h> >>> +#endif >>> + >>> +enum sunxi_dram_type { >>> + SUNXI_DRAM_TYPE_DDR3 = 3, >>> + SUNXI_DRAM_TYPE_DDR4, >>> + SUNXI_DRAM_TYPE_LPDDR3 = 7, >>> + SUNXI_DRAM_TYPE_LPDDR4 >>> +}; >>> + >>> +/* MBUS part is largely the same as in H6, except for one special >>> register */ +struct sunxi_mctl_com_reg { >>> + u32 cr; /* 0x000 control register */ >>> + u8 reserved_0x004[4]; /* 0x004 */ >>> + u32 unk_0x008; /* 0x008 */ >>> + u32 tmr; /* 0x00c timer register */ >>> + u8 reserved_0x010[4]; /* 0x010 */ >>> + u32 unk_0x014; /* 0x014 */ >>> + u8 reserved_0x018[8]; /* 0x018 */ >>> + u32 maer0; /* 0x020 master enable register 0 */ >>> + u32 maer1; /* 0x024 master enable register 1 */ >>> + u32 maer2; /* 0x028 master enable register 2 */ >>> + u8 reserved_0x02c[468]; /* 0x02c */ >>> + u32 bwcr; /* 0x200 bandwidth control register */ >>> + u8 reserved_0x204[12]; /* 0x204 */ >>> + /* >>> + * The last master configured by BSP libdram is at 0x49x, so the >>> + * size of this struct array is set to 41 (0x29) now. >>> + */ >>> + struct { >>> + u32 cfg0; /* 0x0 */ >>> + u32 cfg1; /* 0x4 */ >>> + u8 reserved_0x8[8]; /* 0x8 */ >>> + } master[41]; /* 0x210 + index * 0x10 */ >>> + u8 reserved_0x4a0[96]; /* 0x4a0 */ >>> + u32 unk_0x500; /* 0x500 */ >>> +}; >>> +check_member(sunxi_mctl_com_reg, unk_0x500, 0x500); >>> + >>> +/* >>> + * Controller registers seems to be the same or at least very similar >>> + * to those in H6. >>> + */ >>> +struct sunxi_mctl_ctl_reg { >>> + u32 mstr; /* 0x000 */ >>> + u32 statr; /* 0x004 unused */ >>> + u32 mstr1; /* 0x008 unused */ >>> + u32 unk_0x00c; /* 0x00c */ >> >> This is clken (and the same on H6). It is obvious when looking at the >> standby power-down sequence. > > Where is that sequence? I mostly consulted H6 and Zynq docs where this > register is not explained. I'll update it in next revision.
This is from the H6 ARISC firmware, which has a similar structure to earlier generations with known registers. Cheers, Samuel > Best regards, > Jernej > >> >>> + u32 mrctrl0; /* 0x010 unused */ >>> + u32 mrctrl1; /* 0x014 unused */ >>> + u32 mrstatr; /* 0x018 unused */ >>> + u32 mrctrl2; /* 0x01c unused */ >>> + u32 derateen; /* 0x020 unused */ >>> + u32 derateint; /* 0x024 unused */ >>> + u8 reserved_0x028[8]; /* 0x028 */ >>> + u32 pwrctl; /* 0x030 unused */ >>> + u32 pwrtmg; /* 0x034 unused */ >>> + u32 hwlpctl; /* 0x038 unused */ >>> + u8 reserved_0x03c[20]; /* 0x03c */ >>> + u32 rfshctl0; /* 0x050 unused */ >>> + u32 rfshctl1; /* 0x054 unused */ >>> + u8 reserved_0x058[8]; /* 0x05c */ >>> + u32 rfshctl3; /* 0x060 */ >>> + u32 rfshtmg; /* 0x064 */ >>> + u8 reserved_0x068[104]; /* 0x068 */ >>> + u32 init[8]; /* 0x0d0 */ >>> + u32 dimmctl; /* 0x0f0 unused */ >>> + u32 rankctl; /* 0x0f4 */ >>> + u8 reserved_0x0f8[8]; /* 0x0f8 */ >>> + u32 dramtmg[17]; /* 0x100 */ >>> + u8 reserved_0x144[60]; /* 0x144 */ >>> + u32 zqctl[3]; /* 0x180 */ >>> + u32 zqstat; /* 0x18c unused */ >>> + u32 dfitmg0; /* 0x190 */ >>> + u32 dfitmg1; /* 0x194 */ >>> + u32 dfilpcfg[2]; /* 0x198 unused */ >>> + u32 dfiupd[3]; /* 0x1a0 */ >>> + u32 reserved_0x1ac; /* 0x1ac */ >>> + u32 dfimisc; /* 0x1b0 */ >>> + u32 dfitmg2; /* 0x1b4 unused */ >>> + u32 dfitmg3; /* 0x1b8 unused */ >>> + u32 dfistat; /* 0x1bc */ >>> + u32 dbictl; /* 0x1c0 */ >>> + u8 reserved_0x1c4[60]; /* 0x1c4 */ >>> + u32 addrmap[12]; /* 0x200 */ >>> + u8 reserved_0x230[16]; /* 0x230 */ >>> + u32 odtcfg; /* 0x240 */ >>> + u32 odtmap; /* 0x244 */ >>> + u8 reserved_0x248[8]; /* 0x248 */ >>> + u32 sched[2]; /* 0x250 */ >>> + u8 reserved_0x258[180]; /* 0x258 */ >>> + u32 dbgcmd; /* 0x30c unused */ >>> + u32 dbgstat; /* 0x310 unused */ >>> + u8 reserved_0x314[12]; /* 0x314 */ >>> + u32 swctl; /* 0x320 */ >>> + u32 swstat; /* 0x324 */ >>> + u8 reserved_0x328[7768];/* 0x328 */ >>> + u32 unk_0x2180; /* 0x2180 */ >>> + u8 reserved_0x2184[188];/* 0x2184 */ >>> + u32 unk_0x2240; /* 0x2240 */ >>> + u8 reserved_0x2244[3900];/* 0x2244 */ >>> + u32 unk_0x3180; /* 0x3180 */ >>> + u8 reserved_0x3184[188];/* 0x3184 */ >>> + u32 unk_0x3240; /* 0x3240 */ >>> + u8 reserved_0x3244[3900];/* 0x3244 */ >>> + u32 unk_0x4180; /* 0x4180 */ >>> + u8 reserved_0x4184[188];/* 0x4184 */ >>> + u32 unk_0x4240; /* 0x4240 */ >>> +}; >>> +check_member(sunxi_mctl_ctl_reg, swstat, 0x324); >>> +check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); >>> + >>> +#define MSTR_DEVICETYPE_DDR3 BIT(0) >>> +#define MSTR_DEVICETYPE_LPDDR2 BIT(2) >>> +#define MSTR_DEVICETYPE_LPDDR3 BIT(3) >>> +#define MSTR_DEVICETYPE_DDR4 BIT(4) >>> +#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) >>> +#define MSTR_2TMODE BIT(10) >>> +#define MSTR_BUSWIDTH_FULL (0 << 12) >>> +#define MSTR_BUSWIDTH_HALF (1 << 12) >>> +#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) >>> +#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) >>> + >>> +struct dram_para { >>> + u32 clk; >>> + enum sunxi_dram_type type; >>> + u8 cols; >>> + u8 rows; >>> + u8 ranks; >>> + u8 bus_full_width; >>> +}; >>> + >>> + >>> +static inline int ns_to_t(int nanoseconds) >>> +{ >>> + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; >>> + >>> + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); >>> +} >>> + >>> +void mctl_set_timing_params(struct dram_para *para); >>> + >>> +#endif /* _SUNXI_DRAM_SUN50I_H616_H */ >>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig >>> index 69ab670abf39..1a5497989f04 100644 >>> --- a/arch/arm/mach-sunxi/Kconfig >>> +++ b/arch/arm/mach-sunxi/Kconfig >>> @@ -48,6 +48,46 @@ config DRAM_SUN50I_H6 >>> >>> Select this dram controller driver for some sun50i platforms, >>> like H6. >>> >>> +config DRAM_SUN50I_H616 >>> + bool >>> + help >>> + Select this dram controller driver for some sun50i platforms, >>> + like H616. >>> + >>> +if DRAM_SUN50I_H616 >>> +config DRAM_SUN50I_H616_WRITE_LEVELING >>> + bool "H616 DRAM write leveling" >>> + ---help--- >>> + Select this when DRAM on your H616 board needs write leveling. >>> + >>> +config DRAM_SUN50I_H616_READ_CALIBRATION >>> + bool"H616 DRAM read calibration" >> >> Missing a space here. >> >>> + ---help--- >>> + Select this when DRAM on your H616 board needs read calibration. >>> + >>> +config DRAM_SUN50I_H616_READ_TRAINING >>> + bool "H616 DRAM read training" >>> + ---help--- >>> + Select this when DRAM on your H616 board needs read training. >>> + >>> +config DRAM_SUN50I_H616_WRITE_TRAINING >>> + bool "H616 DRAM write training" >>> + ---help--- >>> + Select this when DRAM on your H616 board needs write training. >>> + >>> +config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION >>> + bool "H616 DRAM bit delay compensation" >>> + ---help--- >>> + Select this when DRAM on your H616 board needs bit delay >>> + compensation. >>> + >>> +config DRAM_SUN50I_H616_UNKNOWN_FEATURE >>> + bool "H616 DRAM unknown feature" >>> + ---help--- >>> + Select this when DRAM on your H616 board needs this unknown >>> + feature. >>> +endif >>> + >>> >>> config SUN6I_P2WI >>> >>> bool "Allwinner sun6i internal P2WI controller" >>> help >>> >>> @@ -423,6 +463,7 @@ config DRAM_CLK >>> >>> MACH_SUN8I_V3S >>> >>> default 672 if MACH_SUN50I >>> default 744 if MACH_SUN50I_H6 >>> >>> + default 720 if MACH_SUN50I_H616 >>> >>> ---help--- >>> Set the dram clock speed, valid range 240 - 480 (prior to sun9i), >>> must be a multiple of 24. For the sun9i (A80), the tested values >>> >>> @@ -439,6 +480,7 @@ endif >>> >>> config DRAM_ZQ >>> >>> int "sunxi dram zq value" >>> >>> + depends on !MACH_SUN50I_H616 >>> >>> default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ >>> >>> MACH_SUN8I_A23 || MACH_SUN8I_A33 || > MACH_SUN8I_A83T >>> >>> default 127 if MACH_SUN7I >>> >>> @@ -456,6 +498,7 @@ config DRAM_ODT_EN >>> >>> default y if MACH_SUN8I_R40 >>> default y if MACH_SUN50I >>> default y if MACH_SUN50I_H6 >>> >>> + default y if MACH_SUN50I_H616 >>> >>> ---help--- >>> Select this to enable dram odt (on die termination). >>> >>> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile >>> index b8aca43d6630..3f081d92f379 100644 >>> --- a/arch/arm/mach-sunxi/Makefile >>> +++ b/arch/arm/mach-sunxi/Makefile >>> @@ -40,4 +40,6 @@ obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o >>> >>> obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ >>> obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o >>> obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/ >>> >>> +obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o >>> +obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/ >>> >>> endif >>> >>> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c >>> b/arch/arm/mach-sunxi/dram_sun50i_h616.c new file mode 100644 >>> index 000000000000..0c86f54b8a73[...]