Giant board is a tiny SBC based on the Adafruit Feather form factor,
created by groboards it contains a SAMA5D2 processor (SAMA5D27),
128 MB of RAM and a microSD card for storage.
Signed-off-by: Greg Gallagher <g...@embeddedgreg.com>
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/at91-sama5d27_giantboard.dts | 128 ++++++++++++
arch/arm/mach-at91/Kconfig | 9 +
board/atmel/sama5d27_giantboard/Kconfig | 15 ++
board/atmel/sama5d27_giantboard/MAINTAINERS | 6 +
board/atmel/sama5d27_giantboard/Makefile | 5 +
.../sama5d27_giantboard/sama5d27_giantboard.c | 182 ++++++++++++++++++
configs/sama5d27_giantboard_defconfig | 93 +++++++++
include/configs/sama5d27_giantboard.h | 136 +++++++++++++
9 files changed, 577 insertions(+)
create mode 100644 arch/arm/dts/at91-sama5d27_giantboard.dts
create mode 100644 board/atmel/sama5d27_giantboard/Kconfig
create mode 100644 board/atmel/sama5d27_giantboard/MAINTAINERS
create mode 100644 board/atmel/sama5d27_giantboard/Makefile
create mode 100644 board/atmel/sama5d27_giantboard/sama5d27_giantboard.c
create mode 100644 configs/sama5d27_giantboard_defconfig
create mode 100644 include/configs/sama5d27_giantboard.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e408f8..23b45290a4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -898,6 +898,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
at91-sama5d27_som1_ek.dtb
+dtb-$(CONFIG_TARGET_SAMA5D27_GIANTBOARD) += \
+ at91-sama5d27_giantboard.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts
b/arch/arm/dts/at91-sama5d27_giantboard.dts
new file mode 100644
index 0000000000..e81ca60ca0
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d27_giantboard.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board
+ *
+ * Copyright (C) 2020 Greg Gallagher <g...@embeddedgreg.com>
+ *
+ * Derived from at91-sama5d27_som1_ek.dts
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.y...@microchip.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Giant Board";
+ compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2",
"atmel,sama5";
+
+ memory {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ chosen {
+ u-boot,dm-pre-reloc;
+ stdout-path = &uart1;
+ };
+
+ ahb {
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default
&pinctrl_sdmmc1_ck_cd_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ apb {
+
+ uart1: serial@f8020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@f8028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ status = "okay";
+ };
+
+ i2c1: i2c@fc028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ pmic@5b {
+ compatible = "active-semi,act8945a";
+ reg = <0x5b>;
+ active-semi,vsel-low;
+ status = "okay";
+ };
+ };
+
+ pit: timer@f8048030 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ sfr: sfr@f8030000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ pioA: gpio@fc038000 {
+ pinctrl {
+
+ pinctrl_sdmmc1_cmd_dat_default:
sdmmc1_cmd_dat_default {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+
<PIN_PA18__SDMMC1_DAT0>,
+
<PIN_PA19__SDMMC1_DAT1>,
+
<PIN_PA20__SDMMC1_DAT2>,
+
<PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_ck_cd_default:
sdmmc1_ck_cd_default {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_uart1_default: uart1_default {
+ pinmux = <PIN_PD2__URXD1>,
+ <PIN_PD3__UTXD1>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD4__TWD1>,
+ <PIN_PD5__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB10__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PA31__GPIO>;
+ bias-disable;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index be1415f909..1837396945 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -183,6 +183,14 @@ config TARGET_SAMA5D2_XPLAINED
select SAMA5D2
select SUPPORT_SPL
+config TARGET_SAMA5D27_GIANTBOARD
+ bool "SAMA5D27 Giant board"
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select CPU_V7A
+ select SUPPORT_SPL
+ select ATMEL_SFR
+
config TARGET_SAMA5D27_SOM1_EK
bool "SAMA5D27 SOM1 EK board"
select BOARD_EARLY_INIT_F
@@ -330,6 +338,7 @@ source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
+source "board/atmel/sama5d27_giantboard/Kconfig"
source "board/atmel/sama5d27_wlsom1_ek/Kconfig"
source "board/atmel/sama5d2_icp/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
diff --git a/board/atmel/sama5d27_giantboard/Kconfig
b/board/atmel/sama5d27_giantboard/Kconfig
new file mode 100644
index 0000000000..6cefb8f689
--- /dev/null
+++ b/board/atmel/sama5d27_giantboard/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D27_GIANTBOARD
+
+config SYS_BOARD
+ default "sama5d27_giantboard"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d27_giantboard"
+
+endif
diff --git a/board/atmel/sama5d27_giantboard/MAINTAINERS
b/board/atmel/sama5d27_giantboard/MAINTAINERS
new file mode 100644
index 0000000000..80bfae01fa
--- /dev/null
+++ b/board/atmel/sama5d27_giantboard/MAINTAINERS
@@ -0,0 +1,6 @@
+SAMA5D27 GIANT BOARD
+M: Greg Gallagher <g...@embeddedgreg.com>
+S: Maintained
+F: board/atmel/sama5d27_giantboard/
+F: include/configs/sama5d27_giantboard.h
+F: configs/sama5d27_giantboard_mmc_defconfig
diff --git a/board/atmel/sama5d27_giantboard/Makefile
b/board/atmel/sama5d27_giantboard/Makefile
new file mode 100644
index 0000000000..d4b2a4d36f
--- /dev/null
+++ b/board/atmel/sama5d27_giantboard/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Greg Gallagher <g...@embeddedgreg.com>
+
+obj-y += sama5d27_giantboard.o
diff --git a/board/atmel/sama5d27_giantboard/sama5d27_giantboard.c
b/board/atmel/sama5d27_giantboard/sama5d27_giantboard.c
new file mode 100644
index 0000000000..d75a9650ad
--- /dev/null
+++ b/board/atmel/sama5d27_giantboard/sama5d27_giantboard.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Greg Gallagher <g...@embeddedgreg.com>
+ *
+ * Derived from sama5d27_som1_ek.c
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.y...@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_USB
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_pda_detect();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart1_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);
/* URXD1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart1_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ if (IS_ENABLED(CONFIG_DEBUG_UART))
+ debug_uart_init();
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ if (IS_ENABLED(CONFIG_CMD_USB))
+ board_usb_hw_init();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_ZQ_LONG |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->rtr = 0x511;
+
+ ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ ddrc_conf(&ddrc_config);
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+ &mpddrc->rd_data_path);
+
+ ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+ writel(0x3, &mpddrc->cal_mr4);
+ writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(40) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ tmp = AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/configs/sama5d27_giantboard_defconfig
b/configs/sama5d27_giantboard_defconfig
new file mode 100644
index 0000000000..4612a75b53
--- /dev/null
+++ b/configs/sama5d27_giantboard_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_AT91=y
+CONFIG_CMDLINE=y
+CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_TARGET_SAMA5D27_GIANTBOARD=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+# CONFIG_MISC_INIT_R is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIBFDT=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_NET is not set
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/include/configs/sama5d27_giantboard.h
b/include/configs/sama5d27_giantboard.h
new file mode 100644
index 0000000000..2311061e1f
--- /dev/null
+++ b/include/configs/sama5d27_giantboard.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D27 Giant Board.
+ *
+ * Copyright (C) 2020 Greg Gallagher <g...@embeddedgreg.com>
+ *
+ * Derived from sama5d27_som1_ek.h
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.y...@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x8000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+/* NAND flash */
+
+/* SPI flash */
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_SD_BOOT
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdtovaddr=0x21800000\0" \
+ "loadaddr=0x22000000\0" \
+ "fdtaddr=0x21000000\0" \
+ "fdtfile=/dtbs/at91-sama5d27_giantboard.dtb\0" \
+ "enable_uboot_overlays=\0" \
+ "dtboverlay=\0" \
+ "dtboverlay1=\0" \
+ "dtboverlay2=\0" \
+ "dtboverlay3=\0" \
+ "dtboverlay4=\0" \
+ "console=ttyS0,115200\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "loadbootenv=load mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
+ "loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \
+ "loadoverlay=load mmc ${mmcdev}:${mmcpart} ${fdtovaddr}
${dtboverlay}\0" \
+ "loadoverlay1=load mmc ${mmcdev}:${mmcpart} ${fdtovaddr}
${dtboverlay1}\0" \
+ "loadoverlay2=load mmc ${mmcdev}:${mmcpart} ${fdtovaddr}
${dtboverlay2}\0" \
+ "loadoverlay3=load mmc ${mmcdev}:${mmcpart} ${fdtovaddr}
${dtboverlay3}\0" \
+ "loadoverlay4=load mmc ${mmcdev}:${mmcpart} ${fdtovaddr}
${dtboverlay4}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "run importbootenv;" \
+ "fi;" \
+ "echo Running default loadzimage ...;" \
+ "if run loadzimage; then " \
+ "run loadfdt;" \
+ "echo Checking for overlays ...;" \
+ "if test -n $enable_uboot_overlays; then " \
+ "fdt addr ${fdtaddr};" \
+ "fdt resize 4096;" \
+ "if test -n $dtboverlay; then " \
+ "run loadoverlay;" \
+ "fdt apply ${fdtovaddr};" \
+ "echo loaded ${dtboverlay};" \
+ "fi;" \
+ "if test -n $dtboverlay1; then " \
+ "run loadoverlay1;" \
+ "fdt apply ${fdtovaddr};" \
+ "echo loaded ${dtboverlay1};" \
+ "fi;" \
+ "if test -n $dtboverlay2; then " \
+ "run loadoverlay2;" \
+ "fdt apply ${fdtovaddr};" \
+ "echo loaded ${dtboverlay2};" \
+ "fi;" \
+ "if test -n $dtboverlay3; then " \
+ "run loadoverlay3;" \
+ "fdt apply ${fdtovaddr};" \
+ "echo loaded ${dtboverlay3};" \
+ "fi;" \
+ "if test -n $dtboverlay4; then " \
+ "run loadoverlay4;" \
+ "fdt apply ${fdtovaddr};" \
+ "echo loaded ${dtboverlay4};" \
+ "fi;" \
+ "fi;" \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;"
+#endif
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
+
+#endif
--
2.25.1
