The CSPI/ECSPI register bits do not differ between newer SoCs, instead
of having multiple copies of the same thing for each iMX SoC, define
the bits in the driver.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Jagan Teki <ja...@amarulasolutions.com>
Cc: Stefano Babic <sba...@denx.de>
---
arch/arm/include/asm/arch-mx25/imx-regs.h | 30 ---------
arch/arm/include/asm/arch-mx31/imx-regs.h | 31 ---------
arch/arm/include/asm/arch-mx35/imx-regs.h | 30 ---------
arch/arm/include/asm/arch-mx5/imx-regs.h | 36 -----------
arch/arm/include/asm/arch-mx6/imx-regs.h | 36 -----------
arch/arm/include/asm/arch-mx7/imx-regs.h | 37 -----------
drivers/spi/mxc_spi.c | 76 +++++++++++++++++++++++
7 files changed, 76 insertions(+), 200 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h
b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 5d0974f3283..57809697c1a 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -269,18 +269,6 @@ struct epit_regs {
u32 cnr; /* Counter register */
};
-/* CSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
- u32 test;
-};
-
#endif
#define ARCH_MXC
@@ -508,24 +496,6 @@ struct cspi_regs {
/*
* CSPI register definitions
*/
-#define MXC_CSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
#define MXC_SPI_BASE_ADDRESSES \
IMX_CSPI1_BASE, \
IMX_CSPI2_BASE, \
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h
b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 9e271d6ea2e..566db549ec6 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -39,17 +39,6 @@ struct clock_control_regs {
u32 pdr2;
};
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
- u32 test;
-};
-
/* IIM control registers */
struct iim_regs {
u32 iim_stat;
@@ -889,26 +878,6 @@ struct esdc_regs {
/*
* CSPI register definitions
*/
-#define MXC_CSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 8)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0x1f
-
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
-
#define MXC_SPI_BASE_ADDRESSES \
0x43fa4000, \
0x50010000, \
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 8ee0754c8e5..35090047c70 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -170,24 +170,6 @@
/*
* CSPI register definitions
*/
-#define MXC_CSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_SMC (1 << 3)
-#define MXC_CSPICTRL_POL (1 << 4)
-#define MXC_CSPICTRL_PHA (1 << 5)
-#define MXC_CSPICTRL_SSCTL (1 << 6)
-#define MXC_CSPICTRL_SSPOL (1 << 7)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 4
-
#define MXC_SPI_BASE_ADDRESSES \
0x43fa4000, \
0x50010000,
@@ -280,18 +262,6 @@ struct gpt_regs {
u32 counter; /* counter */
};
-/* CSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
- u32 test;
-};
-
struct esdc_regs {
u32 esdctl0;
u32 esdcfg0;
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 3d1cc683228..2731b7fb59b 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -204,30 +204,6 @@
/*
* CSPI register definitions
*/
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA 0 /* SCLK phase control */
-#define MXC_CSPICON_POL 4 /* SCLK polarity */
-#define MXC_CSPICON_SSPOL 12 /* SS polarity */
-#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \
@@ -476,18 +452,6 @@ struct srtc_regs {
u32 hpienr; /* 0x38 */
};
-/* CSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 cfg;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
-};
-
struct iim_regs {
u32 stat;
u32 statm;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index ccd48e83055..a8a5bf7a575 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -668,46 +668,10 @@ struct gpc {
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1
(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
-/* ECSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 cfg;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
-};
-
/*
* CSPI register definitions
*/
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
#define SPI_MAX_NUM 4
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA 0 /* SCLK phase control */
-#define MXC_CSPICON_POL 4 /* SCLK polarity */
-#define MXC_CSPICON_SSPOL 12 /* SS polarity */
-#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define MXC_SPI_BASE_ADDRESSES \
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h
b/arch/arm/include/asm/arch-mx7/imx-regs.h
index f37419c07f1..5cab12f30d8 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -842,46 +842,9 @@ struct iomuxc_gpr_base_regs {
u32 gpr[23]; /* 0x000 */
};
-/* ECSPI registers */
-struct cspi_regs {
- u32 rxdata;
- u32 txdata;
- u32 ctrl;
- u32 cfg;
- u32 intr;
- u32 dma;
- u32 stat;
- u32 period;
-};
-
/*
* CSPI register definitions
*/
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN (1 << 0)
-#define MXC_CSPICTRL_MODE (1 << 1)
-#define MXC_CSPICTRL_XCH (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS 0xfff
-#define MXC_CSPICTRL_TC (1 << 7)
-#define MXC_CSPICTRL_RXOVF (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ (1 << 15)
-#define MAX_SPI_BYTES 32
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN 18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA 0 /* SCLK phase control */
-#define MXC_CSPICON_POL 4 /* SCLK polarity */
-#define MXC_CSPICON_SSPOL 12 /* SS polarity */
-#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index e90a06a66de..849808fb916 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -20,6 +20,82 @@
DECLARE_GLOBAL_DATA_PTR;
+/* MX35 and older is CSPI */
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#define MXC_CSPI
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+ u32 test;
+};
+
+#define MXC_CSPICTRL_EN BIT(0)
+#define MXC_CSPICTRL_MODE BIT(1)
+#define MXC_CSPICTRL_XCH BIT(2)
+#define MXC_CSPICTRL_SMC BIT(3)
+#define MXC_CSPICTRL_POL BIT(4)
+#define MXC_CSPICTRL_PHA BIT(5)
+#define MXC_CSPICTRL_SSCTL BIT(6)
+#define MXC_CSPICTRL_SSPOL BIT(7)
+#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_RXOVF BIT(6)
+#define MXC_CSPIPERIOD_32KHZ BIT(15)
+#define MAX_SPI_BYTES 4
+#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_TC BIT(7)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#else /* MX31 */
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_TC BIT(8)
+#define MXC_CSPICTRL_MAXBITS 0x1f
+#endif
+
+#else /* MX51 and newer is ECSPI */
+#define MXC_ECSPI
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 cfg;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+};
+
+#define MXC_CSPICTRL_EN BIT(0)
+#define MXC_CSPICTRL_MODE BIT(1)
+#define MXC_CSPICTRL_XCH BIT(2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC BIT(7)
+#define MXC_CSPICTRL_RXOVF BIT(6)
+#define MXC_CSPIPERIOD_32KHZ BIT(15)
+#define MAX_SPI_BYTES 32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+#endif
+
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in
the
* datasheet, the correct one is in the Freescale's Linux driver */
--
2.29.2
