[PATCH 13/19] video: sunxi: dw-hdmi: move PHY config to appropriate place

[Jernej Skrabec]

Currently sunxi_dw_hdmi_enable() configures PHY timing related
parameters. However, sunxi_dw_hdmi_phy_cfg() is better suited place for
that. Move the code there. This also allows to easier driver expansion
when controller uses different PHY than currently supported (like that
in H6).

Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
---
 drivers/video/sunxi/sunxi_dw_hdmi.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c 
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 483d57293155..4cc175d714ea 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -114,11 +114,13 @@ static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
        writel(0x42494E47, &phy->unscramble);
 }
 
-static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int 
phy_div)
+static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi,
+                                 const struct display_timing *edid,
+                                 int phy_div)
 {
        struct sunxi_hdmi_phy * const phy =
                (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
-       int div = sunxi_dw_hdmi_get_divider(clock);
+       int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ);
        u32 tmp;
 
        /*
@@ -187,6 +189,14 @@ static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, 
uint clock, int phy_div)
                writel(0x0F81C405, &phy->unk2);
                break;
        }
+
+       if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
+               setbits_le32(&phy->pol, 0x200);
+
+       if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
+               setbits_le32(&phy->pol, 0x100);
+
+       setbits_le32(&phy->ctrl, 0xf << 12);
 }
 
 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
@@ -272,7 +282,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi,
        int phy_div;
 
        sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div);
-       sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div);
+       sunxi_dw_hdmi_phy_set(hdmi, edid, phy_div);
 
        return 0;
 }
@@ -304,14 +314,6 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int 
panel_bpp,
 
        sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
 
-       if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
-               setbits_le32(&phy->pol, 0x200);
-
-       if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
-               setbits_le32(&phy->pol, 0x100);
-
-       setbits_le32(&phy->ctrl, 0xf << 12);
-
        /*
         * This is last hdmi access before boot, so scramble addresses
         * again or othwerwise BSP driver won't work. Dummy read is
-- 
2.30.1