This patchset is extracted from "Add Intel Diamond Mesa SoC support" series. We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device and we would like to clean up some code before enable N5X device.
This patchset move duplicated function 'cm_get_qspi_controller_clk_hz' to clock_manager.c and change to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. History: -------- The first version of this patchset is extracted from "Add Intel Diamond Mesa SoC support" series. https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin....@intel.com/ This patchset has dependency on: -------- 1. arm: socfpga: Move Stratix10 and Agilex SPL common code https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin....@intel.com/ 2. Restructure Stratix10 and Agilex handoff code https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly.siew.chin....@intel.com/ Siew Chin Lim (2): arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Changed to store QSPI reference clock in kHz arch/arm/mach-socfpga/clock_manager.c | 16 +++++++-- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ---- arch/arm/mach-socfpga/clock_manager_s10.c | 6 ---- arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 +++ .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - .../include/mach/system_manager_soc64.h | 16 ++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 40 +++++++++++++++++++--- include/configs/socfpga_soc64_common.h | 1 + 8 files changed, 69 insertions(+), 21 deletions(-) -- 2.13.0
