Hi,
On 2/8/21 2:26 PM, Patrick Delaunay wrote:
No more map the reserved region with "no-map" property by marking
the corresponding TLB entries with invalid entry (=0) to avoid
speculative access.
This patch fixes potential issue when predictive access is done by ARM
core.
Signed-off-by: Patrick Delaunay <patrick.delau...@st.com>
Signed-off-by: Patrick Delaunay <patrick.delau...@foss.st.com>
---
(no changes since v1)
arch/arm/include/asm/system.h | 3 +++
arch/arm/lib/cache-cp15.c | 19 +++++++++++++++++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 11fceec4d2..c63ed07f2c 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -444,6 +444,7 @@ static inline void set_cr(unsigned int val)
/* options available for data cache on each page */
enum dcache_option {
+ INVALID_ENTRY = 0,
DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
@@ -474,6 +475,7 @@ enum dcache_option {
* 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate
*/
enum dcache_option {
+ INVALID_ENTRY = 0,
DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
@@ -483,6 +485,7 @@ enum dcache_option {
#define TTB_SECT_AP (3 << 10)
/* options available for data cache on each page */
enum dcache_option {
+ INVALID_ENTRY = 0,
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 8a49e5217c..8a354d364d 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <cpu_func.h>
+#include <lmb.h>
#include <log.h>
#include <asm/system.h>
#include <asm/cache.h>
@@ -101,18 +102,32 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start,
size_t size,
__weak void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
+ struct lmb lmb;
int i;
/* bd->bi_dram is available only after relocation */
if ((gd->flags & GD_FLG_RELOC) == 0)
return;
+ /*
+ * don't allow cache on reserved memory tagged 'no-map' in DT
+ * => avoid speculative access to "secure" data
+ */
+ if (IS_ENABLED(CONFIG_LMB))
+ lmb_init_and_reserve(&lmb, bd, (void *)gd->fdt_blob);
+
debug("%s: bank: %d\n", __func__, bank);
for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
- i++)
- set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+ i++) {
+ if (IS_ENABLED(CONFIG_LMB) &&
+ lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT,
+ LMB_NOMAP))
+ set_section_dcache(i, INVALID_ENTRY);
+ else
+ set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+ }
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
Hi,
After more test on stm32mp15x platform, the patch [6/7] introduced
performance issue for the boot time.
The device tree parsing done in lmb_init_and_reserve() to found the
the reserved memory region with "no-map" tag is done with data
cache deactivated (as it is called before MMU and data cache activation).
This parsing increase the device boot time (several second lost in
stm32mp15).
So I need to sent a update version for this patch [6/7]
But I will also drop this patch patch [7/7] to avoid to increase the
boot time
on other arm platform using cp15.
Regards
Patrick
