On Mon, May 3, 2021 at 5:00 AM Andrey Zhizhikin
<andrey.zhizhi...@leica-geosystems.com> wrote:
>
> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
>
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
>
> Signed-off-by: Andrey Zhizhikin <andrey.zhizhi...@leica-geosystems.com>
> Cc: Stefano Babic <sba...@denx.de>
> Cc: Fabio Estevam <feste...@gmail.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-...@nxp.com>
> Cc: Peng Fan <peng....@nxp.com>
> Cc: Simon Glass <s...@chromium.org>
> Cc: Ye Li <ye...@nxp.com>
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")Reviewed-by: Fabio Estevam <feste...@gmail.com>
