Hi Marek, Thank you for the patch.
On Wed, Apr 28, 2021 at 8:30 PM Marek Vasut <marek.va...@gmail.com> wrote: > > Synchronize RZ/G2 clock tables with Linux 5.12, > commit 9f4ad9e425a1 ("Linux 5.12") . > > Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com> > --- > drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 +++++++++----- > drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 ++++++++ > drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +++++++++ > 3 files changed, 26 insertions(+), 5 deletions(-) > Tested on RZ/G2{EMN} boards. Tested-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> Cheers, Prabhakar > diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > index 1c54eca6c0..ef2bb6d777 100644 > --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > @@ -68,13 +68,18 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { > DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), > DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), > DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), > - DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), > + > + DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, > + CLK_RPCSRC), > + DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, > + R8A774A1_CLK_RPC), > > DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), > > /* Core Clock Outputs */ > - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, > CLK_PLL0, 2, 8), > - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, > CLK_PLL2, 2, 0), > + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, > CLK_PLL0, 2, 8), > + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, > CLK_PLL2, 2, 0), > DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), > DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), > DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), > @@ -99,7 +104,6 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { > DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078), > DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268), > DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c), > - DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC, 0x238), > > DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), > DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), > @@ -203,7 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = { > DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2), > DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4), > DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4), > - DEF_MOD("rpc", 917, R8A774A1_CLK_RPC), > + DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), > DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), > DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), > DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP), > diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c > b/drivers/clk/renesas/r8a774b1-cpg-mssr.c > index 03851d0b5a..a8b242dc47 100644 > --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c > @@ -39,6 +39,7 @@ enum clk_ids { > CLK_S2, > CLK_S3, > CLK_SDSRC, > + CLK_RPCSRC, > CLK_RINT, > > /* Module Clocks */ > @@ -64,6 +65,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = { > DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), > DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), > DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), > + > + DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, > + CLK_RPCSRC), > + DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, > + R8A774B1_CLK_RPC), > > DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), > > @@ -195,6 +202,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = { > DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), > DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), > DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4), > + DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), > DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), > DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), > DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP), > diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > index 37a7123f73..6e9558a107 100644 > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > @@ -44,6 +44,7 @@ enum clk_ids { > CLK_S2, > CLK_S3, > CLK_SDSRC, > + CLK_RPCSRC, > CLK_RINT, > CLK_OCO, > > @@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = { > DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), > DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), > > + DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), > + > + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, > + CLK_RPCSRC), > + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, > + R8A774C0_CLK_RPC), > + > DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), > > DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), > @@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = { > DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2), > DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4), > DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4), > + DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2), > DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), > DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), > DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP), > -- > 2.30.2 >