> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ() > macro, which expands the value provided to the Hz range without taking into > account the precise Hz setting. This causes the frequency of 266 MHz not ot > be found in the imx8mm_fracpll_tbl, since it is entered there with a > precise Hz value. This in turn causes the boot hang in SPL, as proper DDR > fracpll frequency cannot be determined. > Correct the value in imx8mm_fracpll_tbl to match the one expanded by > MHZ(266) macro, rounding it down to MHz range only. > Signed-off-by: Andrey Zhizhikin <andrey.zhizhi...@leica-geosystems.com> > Cc: Stefano Babic <sba...@denx.de> > Cc: Fabio Estevam <feste...@gmail.com> > Cc: "NXP i.MX U-Boot Team" <uboot-...@nxp.com> > Cc: Peng Fan <peng....@nxp.com> > Cc: Simon Glass <s...@chromium.org> > Cc: Ye Li <ye...@nxp.com> > Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m") > Reviewed-by: Fabio Estevam <feste...@gmail.com> Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =====================================================================