> From: Bin Meng <bmeng...@gmail.com> > Sent: Friday, June 04, 2021 1:51 PM > To: Rick Jian-Zhi Chen(陳建志) <r...@andestech.com>; Leo Yu-Chi Liang(梁育齊) > <ycli...@andestech.com>; U-Boot Mailing List <u-boot@lists.denx.de> > Subject: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in > 32-bit > > All the device nodes that refer to plic0 as their interrupt parent have 2 > cells encoded in their interrupts property, but plic0 only provides 1 cell in > #interrupt-cells which is incorrect. > > Signed-off-by: Bin Meng <bmeng...@gmail.com> > --- > > arch/riscv/dts/ae350_32.dts | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rick Chen <r...@andestech.com>
