On Sat, 19 Jun 2021 17:20:05 +0800
Icenowy Zheng <icen...@aosc.io> wrote:

> There's now a sun20i family in sunxi, which uses RISC-V CPU.
> 
> Add support for making eGON.BT0 image for RISC-V.
> 
> Signed-off-by: Icenowy Zheng <icen...@aosc.io>

Compared against the RISC-V manual.

Reviewed-by: Andre Przywara <andre.przyw...@arm.com>

Cheers,
Andre

> ---
> Changes in v2:
> - Removed changes that should belong to the previous patch in v1.
> 
>  tools/sunxi_egon.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
> index 062c9bc151..836e99a6e6 100644
> --- a/tools/sunxi_egon.c
> +++ b/tools/sunxi_egon.c
> @@ -29,6 +29,7 @@ static int egon_check_params(struct image_tool_params 
> *params)
>        */
>       switch (arch) {
>       case IH_ARCH_ARM:
> +     case IH_ARCH_RISCV:
>               break;
>       default:
>               return EXIT_FAILURE;
> @@ -60,6 +61,10 @@ static int egon_verify_header(unsigned char *ptr, int 
> image_size,
>               if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 
> 0xea000000)
>                       return EXIT_FAILURE;
>               break;
> +     case IH_ARCH_RISCV:
> +             if ((le32_to_cpu(header->b_instruction) & 0x00000fff) != 
> 0x0000006f)
> +                     return EXIT_FAILURE;
> +             break;
>       default:
>               return EXIT_FAILURE; /* Unknown architecture */
>       }
> @@ -128,6 +133,24 @@ static void egon_set_header(void *buf, struct stat 
> *sbuf, int infd,
>               value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2);
>               header->b_instruction = cpu_to_le32(value);
>               break;
> +     case IH_ARCH_RISCV:
> +             /*
> +              * Generate a RISC-V JAL instruction with rd=x0
> +              * (pseudo instruction J, jump without side effects).
> +              *
> +              * The following weird bit operation maps imm[20]
> +              * to inst[31], imm[10:1] to inst[30:21],
> +              * imm[11] to inst[20], imm[19:12] to inst[19:12],
> +              * and imm[0] is dropped (because 1-byte RISC-V instruction
> +              * is not allowed).
> +              */
> +             value = 0x0000006f |
> +                     ((sizeof(struct boot_file_head) & 0x00100000) << 11) |
> +                     ((sizeof(struct boot_file_head) & 0x000007fe) << 20) |
> +                     ((sizeof(struct boot_file_head) & 0x00000800) << 9) |
> +                     ((sizeof(struct boot_file_head) & 0x000ff000) << 0);
> +             header->b_instruction = cpu_to_le32(value);
> +             break;
>       }
>  
>       memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));

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