[PATCH 1/4] drivers: ddr: util.c: Fix divide by zero issue

[Priyanka Singh]

Fix possible divide by zero issue in get_memory_clk_period_ps
by adding a check

Signed-off-by: Priyanka Singh <priyanka.si...@nxp.com>
---
 drivers/ddr/fsl/util.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ac4f8d2732..43cb01804b 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -75,10 +76,13 @@ unsigned int get_memory_clk_period_ps(const unsigned int 
ctrl_num)
 
        /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
        unsigned long long rem, mclk_ps = ULL_2E12;
-
-       /* Now perform the big divide, the result fits in 32-bits */
-       rem = do_div(mclk_ps, data_rate);
-       result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+       if (data_rate) {
+               /* Now perform the big divide, the result fits in 32-bits */
+               rem = do_div(mclk_ps, data_rate);
+               result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+       } else {
+               result = 0;
+       }
 
        return result;
 }
-- 
2.17.1