On Sat, Sep 4, 2021 at 4:37 PM Heinrich Schuchardt <xypron.g...@gmx.de> wrote: > > To make analyzing exceptions easier output the code that leads to it. > We already do the same on the ARM platform. > > Here is an example: > > => exception ebreak > Unhandled exception: Breakpoint > EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 > EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted > > Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) > > To disassemble the code we can use the decodecode script: > > $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ > CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode > > Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) > All code > ======== > 0: 2785 addiw a5,a5,1 > 2: 07a00693 li a3,122 > 6: fef6dce3 bge a3,a5,0xfffffffffffffffe > a: 47a5 li a5,9 > c: 00e7d563 bge a5,a4,0x16 > 10:* 9002 ebreak <-- trapping instruction > ... > > Code starting with the faulting instruction > =========================================== > 0: 9002 ebreak > ... > > As it is not always clear if the first 16 bits are at the start or in the > middle of a 32bit instruction it may become necessary to strip the first > u16 from the output before calling decodecode to get the correct > disassembled code. > > Signed-off-by: Heinrich Schuchardt <xypron.g...@gmx.de> > --- > v2: > remove support for instructions longer than 32 bit as these are > not yet specified > --- > arch/riscv/lib/interrupts.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) >
Reviewed-by: Bin Meng <bmeng...@gmail.com>