Andre Schwarz <andre.schw...@matrix-vision.de> wrote on 2010/11/04 14:32:15:
>
> Jocke,
>
> [snip]
>
> > still -E_TOO_LITTLE_INFO:
> >
>
> sorry - thought it was clear already.
>
> > "include weather booted from NAND or NOR, CPU type(e300cX) and
> > what reset vector is used."
> >
> CPU: e300c4, MPC8379, Rev: 2.1 at 600 MHz, CSB: 400 MHz
>
> - Boot from NOR Flash
> - HRCW from I2C EEPROM
> - Reset Vector 0x100, i.e. low boot.
OK, almost the same as me, but I got a:
CPU: e300c2, MPC8321, Rev: 1.1 at 266.664 MHz, CSB: 133.332 MHz
However, I think I just found the problem.
My tree is a bit messy now so no patch but it will be:
Stick an isync (or sync) in
map_flash_by_law1
....
stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
isync //HERE !! HERE !! HERE
blr
I am guessing it takes a while for the stw r4, LBLAWAR1(r3)
to hit the HW so one must wait for it, not sure what is
best though, sync or isync?
There is nothing wrong with my reset vector
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