On Sun, Sep 12, 2021 at 9:55 PM Gaurav Jain <gaurav.j...@nxp.com> wrote: > > Hello Tim, > > > -----Original Message----- > > From: Tim Harvey <thar...@gateworks.com> > > Sent: Friday, September 10, 2021 8:17 PM > > To: Gaurav Jain <gaurav.j...@nxp.com> > > Cc: u-boot <u-boot@lists.denx.de>; Stefano Babic <sba...@denx.de>; Fabio > > Estevam <feste...@gmail.com>; Peng Fan <peng....@nxp.com>; Simon Glass > > <s...@chromium.org>; Priyanka Jain <priyanka.j...@nxp.com>; Ye Li > > <ye...@nxp.com>; Horia Geanta <horia.gea...@nxp.com>; Ji Luo > > <ji....@nxp.com>; Franck Lenormand <franck.lenorm...@nxp.com>; Silvano Di > > Ninno <silvano.dini...@nxp.com>; Sahil Malhotra <sahil.malho...@nxp.com>; > > Pankaj Gupta <pankaj.gu...@nxp.com>; Varun Sethi <v.se...@nxp.com>; dl- > > uboot-imx <uboot-...@nxp.com>; Shengzhou Liu <shengzhou....@nxp.com>; > > Mingkai Hu <mingkai...@nxp.com>; Rajesh Bhagat <rajesh.bha...@nxp.com>; > > Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Wasim Khan > > <wasim.k...@nxp.com>; Alison Wang <alison.w...@nxp.com>; Pramod > > Kumar <pramod.kuma...@nxp.com>; Andy Tang <andy.t...@nxp.com>; > > Adrian Alonso <adrian.alo...@nxp.com>; Vladimir Oltean <olte...@gmail.com> > > Subject: [EXT] Re: [PATCH v2 03/15] i.MX8M: crypto: updated device tree for > > supporting DM in SPL > > > > Caution: EXT Email > > > > On Fri, Sep 3, 2021 at 12:04 AM Gaurav Jain <gaurav.j...@nxp.com> wrote: > > > > > > disabled use of JR0 in SPL and uboot, as JR0 is reserved for secure > > > boot. > > > > > > Signed-off-by: Gaurav Jain <gaurav.j...@nxp.com> > > > --- > > > arch/arm/dts/imx8mm-evk-u-boot.dtsi | 18 +++++++++++++++++- > > > arch/arm/dts/imx8mm.dtsi | 1 + > > > arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 18 +++++++++++++++++- > > > arch/arm/dts/imx8mn.dtsi | 1 + > > > arch/arm/dts/imx8mp-evk-u-boot.dtsi | 18 +++++++++++++++++- > > > arch/arm/dts/imx8mp.dtsi | 1 + > > > arch/arm/dts/imx8mq.dtsi | 1 + > > > 7 files changed, 55 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi > > > b/arch/arm/dts/imx8mm-evk-u-boot.dtsi > > > index f200afac9f..3c2502cbba 100644 > > > --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi > > > +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi > > > @@ -1,6 +1,6 @@ > > > // SPDX-License-Identifier: GPL-2.0+ > > > /* > > > - * Copyright 2019 NXP > > > + * Copyright 2019, 2021 NXP > > > */ > > > > > > #include "imx8mm-u-boot.dtsi" > > > @@ -72,6 +72,22 @@ > > > u-boot,dm-spl; > > > }; > > > > > > +&crypto { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr0 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr1 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr2 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > &usdhc1 { > > > u-boot,dm-spl; > > > }; > > > diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index > > > b142b80734..009999bf3a 100644 > > > --- a/arch/arm/dts/imx8mm.dtsi > > > +++ b/arch/arm/dts/imx8mm.dtsi > > > @@ -824,6 +824,7 @@ > > > compatible = > > > "fsl,sec-v4.0-job-ring"; > > > reg = <0x1000 0x1000>; > > > interrupts = <GIC_SPI 105 > > > IRQ_TYPE_LEVEL_HIGH>; > > > + status = "disabled"; > > > }; > > > > > > sec_jr1: jr@2000 { diff --git > > > a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi > > > b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi > > > index 1d3844437d..b462d24eb2 100644 > > > --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi > > > +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi > > > @@ -1,6 +1,6 @@ > > > // SPDX-License-Identifier: GPL-2.0+ > > > /* > > > - * Copyright 2019 NXP > > > + * Copyright 2019, 2021 NXP > > > */ > > > > > > / { > > > @@ -104,6 +104,22 @@ > > > u-boot,dm-spl; > > > }; > > > > > > +&crypto { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr0 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr1 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr2 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > &usdhc1 { > > > u-boot,dm-spl; > > > }; > > > diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index > > > edcb415b53..1820a5af37 100644 > > > --- a/arch/arm/dts/imx8mn.dtsi > > > +++ b/arch/arm/dts/imx8mn.dtsi > > > @@ -822,6 +822,7 @@ > > > compatible = > > > "fsl,sec-v4.0-job-ring"; > > > reg = <0x1000 0x1000>; > > > interrupts = <GIC_SPI 105 > > > IRQ_TYPE_LEVEL_HIGH>; > > > + status = "disabled"; > > > }; > > > > > > sec_jr1: jr@2000 { diff --git > > > a/arch/arm/dts/imx8mp-evk-u-boot.dtsi > > > b/arch/arm/dts/imx8mp-evk-u-boot.dtsi > > > index 2abcf1f03d..5415d5b617 100644 > > > --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi > > > +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi > > > @@ -1,6 +1,6 @@ > > > // SPDX-License-Identifier: GPL-2.0+ > > > /* > > > - * Copyright 2019 NXP > > > + * Copyright 2019, 2021 NXP > > > */ > > > > > > #include "imx8mp-u-boot.dtsi" > > > @@ -67,6 +67,22 @@ > > > u-boot,dm-spl; > > > }; > > > > > > +&crypto { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr0 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr1 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > +&sec_jr2 { > > > + u-boot,dm-spl; > > > +}; > > > + > > > &i2c1 { > > > u-boot,dm-spl; > > > }; > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index > > > c2d51a46cb..57b01c3a57 100644 > > > --- a/arch/arm/dts/imx8mp.dtsi > > > +++ b/arch/arm/dts/imx8mp.dtsi > > > @@ -624,6 +624,7 @@ > > > compatible = > > > "fsl,sec-v4.0-job-ring"; > > > reg = <0x1000 0x1000>; > > > interrupts = <GIC_SPI 105 > > > IRQ_TYPE_LEVEL_HIGH>; > > > + status = "disabled"; > > > }; > > > > > > sec_jr1: jr@2000 { diff --git > > > a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index > > > a44f729d0e..ecab44ca13 100644 > > > --- a/arch/arm/dts/imx8mq.dtsi > > > +++ b/arch/arm/dts/imx8mq.dtsi > > > @@ -955,6 +955,7 @@ > > > compatible = > > > "fsl,sec-v4.0-job-ring"; > > > reg = <0x1000 0x1000>; > > > interrupts = <GIC_SPI 105 > > > IRQ_TYPE_LEVEL_HIGH>; > > > + status = "disabled"; > > > }; > > > > > > sec_jr1: jr@2000 { > > > -- > > > 2.17.1 > > > > > > > Is there a reason these need to be in board specific dts vs the base ones > > that are > > included by all the boards? > > > > We have different clock for different boards and we want to control job rings > for each board separately. >
Gaurav, I agree that imx8mm, imx8mn, imx8mp all have different clocks but you are setting adding nodes to 'board' specific u-boot.dtsi's that include common files where instead they should go. For example arch/arm/dts/imx8mm-evk-u-boot.dtsi includes 'imx8mm-u-boot.dtsi' so you should be adding the crypto/sec_jr0/sec_jr1/sec_jr2 nodes there. Similarly arch/arm/dts/imx8mp-evk-u-boot.dtsi includes 'imx8mp-u-boot.dtsi' so they should go there. The addition of the common imx8mm-u-boot.dtsi and imx8mp-u-boot.dtsi is rather recent so you may not have seen that. Additionally there doesn't appear to be a common imx8mn-u-boot.dtsi yet and one should be created. Best regards, Tim