On 7/22/21 1:30 AM, Icenowy Zheng wrote:
> Currently only a subset of clocks/resets (similar to other SoCs) are
> supported.
>
> Signed-off-by: Icenowy Zheng <icen...@sipeed.com>
Reviewed-by: Samuel Holland <sam...@sholland.org>
> ---
> drivers/clk/sunxi/Kconfig | 7 +++
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk_r329.c | 94 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 102 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk_r329.c
>
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> index bf084fa7a8..8dd3be4683 100644
> --- a/drivers/clk/sunxi/Kconfig
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -86,6 +86,13 @@ config CLK_SUN50I_H616
> This enables common clock driver support for platforms based
> on Allwinner H616 SoC.
>
> +config CLK_SUN50I_R329
> + bool "Clock driver for Allwinner R329"
> + default MACH_SUN50I_R329
> + help
> + This enables common clock driver support for platforms based
> + on Allwinner R329 SoC.
> +
> config CLK_SUN50I_A64
> bool "Clock driver for Allwinner A64"
> default MACH_SUN50I
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 4f9282a8b9..050f7ecc46 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -19,4 +19,5 @@ obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
> obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
> obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
> obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
> +obj-$(CONFIG_CLK_SUN50I_R329) += clk_r329.o
> obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
> diff --git a/drivers/clk/sunxi/clk_r329.c b/drivers/clk/sunxi/clk_r329.c
> new file mode 100644
> index 0000000000..17157214b6
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk_r329.c
> @@ -0,0 +1,94 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 Sipeed
> + * Based on clk_h616.c, which is:
> + * Copyright (C) 2021 Jernej Skrabec <jernej.skra...@siol.net>
> + */
> +
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <asm/arch/ccu.h>
This will need to be updated when you rebase:
#include <clk/sunxi.h>
Regards,
Samuel
> +#include <dt-bindings/clock/sun50i-r329-ccu.h>
> +#include <dt-bindings/reset/sun50i-r329-ccu.h>
> +#include <linux/bitops.h>
> +
> +static struct ccu_clk_gate r329_gates[] = {
> + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> +
> + [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
> + [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
> + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
> + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
> +
> + [CLK_SPI0] = GATE(0x940, BIT(31)),
> + [CLK_SPI1] = GATE(0x944, BIT(31)),
> +
> + [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
> + [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
> +
> + [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
> +
> + [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
> + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
> +
> + [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
> + [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
> +
> + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
> + [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
> + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
> + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
> +};
> +
> +static struct ccu_reset r329_resets[] = {
> + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
> + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
> +
> + [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
> + [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
> + [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
> + [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
> +
> + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
> + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
> +
> + [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
> +
> + [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
> +
> + [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
> +
> + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
> + [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
> + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
> + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
> +};
> +
> +static const struct ccu_desc r329_ccu_desc = {
> + .gates = r329_gates,
> + .resets = r329_resets,
> +};
> +
> +static int r329_clk_bind(struct udevice *dev)
> +{
> + return sunxi_reset_bind(dev, ARRAY_SIZE(r329_resets));
> +}
> +
> +static const struct udevice_id r329_ccu_ids[] = {
> + { .compatible = "allwinner,sun50i-r329-ccu",
> + .data = (ulong)&r329_ccu_desc },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_sun50i_r329) = {
> + .name = "sun50i_r329_ccu",
> + .id = UCLASS_CLK,
> + .of_match = r329_ccu_ids,
> + .priv_auto = sizeof(struct ccu_priv),
> + .ops = &sunxi_clk_ops,
> + .probe = sunxi_clk_probe,
> + .bind = r329_clk_bind,
> +};
>
