On Tue, 4 Jan 2022 15:57:49 +0100 Marek Behún <ka...@kernel.org> wrote:
> From: Marek Behún <marek.be...@nic.cz> > > Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async > mode"), Asynchornous Mode was only used when the CPU Subsystem Clock > Options[4:0] field in the SAR1 register was set to value 0x13: CPU at > 2 GHz and DDR at 933 MHz. > > Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async > mode") added support for Asynchornous Modes with frequencies other than > 933 MHz (but at least 467 MHz), but the code it added to check for > whether Asynchornous Mode should be used is wrong: it checks whether the > frequency setting in board DDR topology map is set to value other than > MV_DDR_FREQ_SAR. > > Thus boards which define a specific value, greater than 400 MHz, for DDR > frequency in their board topology (e.g. Turris Omnia defines > MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that > commit. > > The A38x Functional Specification, section 10.12 DRAM Clocking, says: > In Synchornous mode, the DRAM and CPU clocks are edge aligned and run > in 1:2 or 1:3 CPU to DRAM frequency ratios. > > Change the check for whether Asynchornous Mode should be used according > to this explanation in Functional Specification. > > Signed-off-by: Marek Behún <marek.be...@nic.cz> I forgot to mention that we discovered this on Turris Omnia by comparing DDR speed with the time mtest 10000000 10100000 0 1 command. In Asynchornous Mode this takes ~27 seconds, in Synchronous mode ~22 seconds. Marek