On Tue, Jan 11, 2022 at 01:25:39PM +0530, Aswath Govindraju wrote: > The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration in automotive ADAS applications and > industrial applications requiring AI at the network edge. This SoC extends > the Jacinto 7 family of SoCs with focus on lowering system costs and power > while providing interfaces, memory architecture and compute performance for > single and multi-sensor applications. > > Some highlights of this SoC are: > > * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable > dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x > floating point Vector DSP. > * 3D GPU: Automotive grade IMG BXS-4-64 > * Vision Processing Accelerator (VPAC) with image signal processor and > Depth and Motion Processing Accelerator (DMPAC) > * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. > * Two Ethernet ports with RGMII support. > * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, > * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, > QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL > management. > > See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) > for further details: http://www.ti.com/lit/pdf/spruj28 > > Introduce basic support for the J721S2 SoC. > > Signed-off-by: Aswath Govindraju <a-govindr...@ti.com> > Signed-off-by: Vignesh Raghavendra <vigne...@ti.com> > Signed-off-by: Nishanth Menon <n...@ti.com> > --- > arch/arm/dts/k3-j721s2-main.dtsi | 937 +++++++++++++++++++++++++ > arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 302 ++++++++ > arch/arm/dts/k3-j721s2.dtsi | 167 +++++
What's the status of these dts files with upstream? -- Tom
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