On 2022-01-28 19:19, Aurelien Jarno wrote: > On 2022-01-28 19:03, Heinrich Schuchardt wrote: > > On 1/28/22 14:47, Alexandre Ghiti wrote: > > > The following description is copied from the equivalent patch for the > > > Linux Kernel proposed by Aurelien Jarno: > > > > > > From version 2.38, binutils default to ISA spec version 20191213. This > > > means that the csr read/write (csrr*/csrw*) instructions and fence.i > > > instruction has separated from the `I` extension, become two standalone > > > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > > > this causes the following build failure: > > > > > > arch/riscv/cpu/mtrap.S: Assembler messages: > > > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' > > > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' > > > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' > > > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' > > > > I tried to build qemu-riscv64_smode_defconfig. With your patch I get > > > > arch/riscv/cpu/cpu.c: Assembler messages: > > arch/riscv/cpu/cpu.c:94: Error: unrecognized opcode `csrs sstatus,a5' > > arch/riscv/cpu/cpu.c:95: Error: unrecognized opcode `csrw 0x003,0' > > > > The build flag used is -march=rv64imac. > > > > My toolchain is: > > binutils 2.37.90.20220126-0ubuntu1 > > riscv64-linux-gnu-gcc (Ubuntu 10.3.0-8ubuntu1) 10.3.0 > > > > This GCC does not support _zicsr_zifencei: > > cc1: error: ‘-march=rv64imac_zicsr_zifencei’: unsupported ISA subset ‘z > > > > Could it be that the GCC is too old for the new binutils? > > When was the z subset added to GCC? > > Yes, GCC 11 is the minimum version that understand those extensions.
GCC 11 is also required to support the not recommended alternative fix -misa-spec=2.2. If you need to support GCC 10, it seems that the only option is to build binutils with --with-isa-spec=2.2. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
