On Sat, 29 Jan 2022 10:23:08 -0500 Jesse Taube <mr.bossman...@gmail.com> wrote:
> From: Icenowy Zheng <icen...@aosc.io> > > Add device tree files for suniv and > Lichee Pi Nano it is a board based on F1C100s. > dt-bindings/dts are synced with 5.16.0 Many thanks, that looks correct now. Confirmed that the files match exactly the Linux tree. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io> > Signed-off-by: Jesse Taube <mr.bossman...@gmail.com> Reviewed-by: Andre Przywara <andre.przyw...@arm.com> Cheers, Andre > --- > V1->V2: > * Sync with Linux > * Re-add MMC node > V2->V3: > * Add ifndef for mmc in sunxi-u-boot.dtsi > * Direct copy of all files from linux > * Squash dt-bindings here > --- > arch/arm/dts/Makefile | 2 + > arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 26 ++++ > arch/arm/dts/suniv-f1c100s.dtsi | 144 ++++++++++++++++++ > arch/arm/dts/sunxi-u-boot.dtsi | 2 + > include/dt-bindings/clock/suniv-ccu-f1c100s.h | 70 +++++++++ > include/dt-bindings/reset/suniv-ccu-f1c100s.h | 38 +++++ > 6 files changed, 282 insertions(+) > create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts > create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi > create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h > create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 453e2fd1a9..07030deeca 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -497,6 +497,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ > stm32h743i-eval.dtb \ > stm32h750i-art-pi.dtb > > +dtb-$(CONFIG_MACH_SUNIV) += \ > + suniv-f1c100s-licheepi-nano.dtb > dtb-$(CONFIG_MACH_SUN4I) += \ > sun4i-a10-a1000.dtb \ > sun4i-a10-ba10-tvbox.dtb \ > diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts > b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts > new file mode 100644 > index 0000000000..a1154e6c7c > --- /dev/null > +++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts > @@ -0,0 +1,26 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR X11) > +/* > + * Copyright 2018 Icenowy Zheng <icen...@aosc.io> > + */ > + > +/dts-v1/; > +#include "suniv-f1c100s.dtsi" > + > +/ { > + model = "Lichee Pi Nano"; > + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_pe_pins>; > + status = "okay"; > +}; > diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi > new file mode 100644 > index 0000000000..6100d3b75f > --- /dev/null > +++ b/arch/arm/dts/suniv-f1c100s.dtsi > @@ -0,0 +1,144 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR X11) > +/* > + * Copyright 2018 Icenowy Zheng <icen...@aosc.io> > + * Copyright 2018 Mesih Kilinc <mesihkil...@gmail.com> > + */ > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&intc>; > + > + clocks { > + osc24M: clk-24M { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: clk-32k { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + }; > + > + cpus { > + cpu { > + compatible = "arm,arm926ej-s"; > + device_type = "cpu"; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram-controller@1c00000 { > + compatible = "allwinner,suniv-f1c100s-system-control", > + "allwinner,sun4i-a10-system-control"; > + reg = <0x01c00000 0x30>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram_d: sram@10000 { > + compatible = "mmio-sram"; > + reg = <0x00010000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x00010000 0x1000>; > + > + otg_sram: sram-section@0 { > + compatible = > "allwinner,suniv-f1c100s-sram-d", > + > "allwinner,sun4i-a10-sram-d"; > + reg = <0x0000 0x1000>; > + status = "disabled"; > + }; > + }; > + }; > + > + ccu: clock@1c20000 { > + compatible = "allwinner,suniv-f1c100s-ccu"; > + reg = <0x01c20000 0x400>; > + clocks = <&osc24M>, <&osc32k>; > + clock-names = "hosc", "losc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + intc: interrupt-controller@1c20400 { > + compatible = "allwinner,suniv-f1c100s-ic"; > + reg = <0x01c20400 0x400>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + pio: pinctrl@1c20800 { > + compatible = "allwinner,suniv-f1c100s-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <38>, <39>, <40>; > + clocks = <&ccu 37>, <&osc24M>, <&osc32k>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + > + uart0_pe_pins: uart0-pe-pins { > + pins = "PE0", "PE1"; > + function = "uart0"; > + }; > + }; > + > + timer@1c20c00 { > + compatible = "allwinner,suniv-f1c100s-timer"; > + reg = <0x01c20c00 0x90>; > + interrupts = <13>; > + clocks = <&osc24M>; > + }; > + > + wdt: watchdog@1c20ca0 { > + compatible = "allwinner,suniv-f1c100s-wdt", > + "allwinner,sun4i-a10-wdt"; > + reg = <0x01c20ca0 0x20>; > + }; > + > + uart0: serial@1c25000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c25000 0x400>; > + interrupts = <1>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu 38>; > + resets = <&ccu 24>; > + status = "disabled"; > + }; > + > + uart1: serial@1c25400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c25400 0x400>; > + interrupts = <2>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu 39>; > + resets = <&ccu 25>; > + status = "disabled"; > + }; > + > + uart2: serial@1c25800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c25800 0x400>; > + interrupts = <3>; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&ccu 40>; > + resets = <&ccu 26>; > + status = "disabled"; > + }; > + }; > +}; > diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi > index f2d7361b84..0f573e6d7a 100644 > --- a/arch/arm/dts/sunxi-u-boot.dtsi > +++ b/arch/arm/dts/sunxi-u-boot.dtsi > @@ -12,7 +12,9 @@ > > / { > aliases { > +#ifndef CONFIG_MACH_SUNIV > mmc0 = &mmc0; > +#endif > #if CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 > mmc1 = &mmc2; > #endif > diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h > b/include/dt-bindings/clock/suniv-ccu-f1c100s.h > new file mode 100644 > index 0000000000..f5ac155c9c > --- /dev/null > +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h > @@ -0,0 +1,70 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + * > + * Copyright (c) 2018 Icenowy Zheng <icen...@aosc.xyz> > + * > + */ > + > +#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ > +#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ > + > +#define CLK_CPU 11 > + > +#define CLK_BUS_DMA 14 > +#define CLK_BUS_MMC0 15 > +#define CLK_BUS_MMC1 16 > +#define CLK_BUS_DRAM 17 > +#define CLK_BUS_SPI0 18 > +#define CLK_BUS_SPI1 19 > +#define CLK_BUS_OTG 20 > +#define CLK_BUS_VE 21 > +#define CLK_BUS_LCD 22 > +#define CLK_BUS_DEINTERLACE 23 > +#define CLK_BUS_CSI 24 > +#define CLK_BUS_TVD 25 > +#define CLK_BUS_TVE 26 > +#define CLK_BUS_DE_BE 27 > +#define CLK_BUS_DE_FE 28 > +#define CLK_BUS_CODEC 29 > +#define CLK_BUS_SPDIF 30 > +#define CLK_BUS_IR 31 > +#define CLK_BUS_RSB 32 > +#define CLK_BUS_I2S0 33 > +#define CLK_BUS_I2C0 34 > +#define CLK_BUS_I2C1 35 > +#define CLK_BUS_I2C2 36 > +#define CLK_BUS_PIO 37 > +#define CLK_BUS_UART0 38 > +#define CLK_BUS_UART1 39 > +#define CLK_BUS_UART2 40 > + > +#define CLK_MMC0 41 > +#define CLK_MMC0_SAMPLE 42 > +#define CLK_MMC0_OUTPUT 43 > +#define CLK_MMC1 44 > +#define CLK_MMC1_SAMPLE 45 > +#define CLK_MMC1_OUTPUT 46 > +#define CLK_I2S 47 > +#define CLK_SPDIF 48 > + > +#define CLK_USB_PHY0 49 > + > +#define CLK_DRAM_VE 50 > +#define CLK_DRAM_CSI 51 > +#define CLK_DRAM_DEINTERLACE 52 > +#define CLK_DRAM_TVD 53 > +#define CLK_DRAM_DE_FE 54 > +#define CLK_DRAM_DE_BE 55 > + > +#define CLK_DE_BE 56 > +#define CLK_DE_FE 57 > +#define CLK_TCON 58 > +#define CLK_DEINTERLACE 59 > +#define CLK_TVE2_CLK 60 > +#define CLK_TVE1_CLK 61 > +#define CLK_TVD 62 > +#define CLK_CSI 63 > +#define CLK_VE 64 > +#define CLK_CODEC 65 > +#define CLK_AVS 66 > + > +#endif > diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h > b/include/dt-bindings/reset/suniv-ccu-f1c100s.h > new file mode 100644 > index 0000000000..6a4b4385fe > --- /dev/null > +++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h > @@ -0,0 +1,38 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + * > + * Copyright (C) 2018 Icenowy Zheng <icen...@aosc.xyz> > + * > + */ > + > +#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ > +#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ > + > +#define RST_USB_PHY0 0 > +#define RST_BUS_DMA 1 > +#define RST_BUS_MMC0 2 > +#define RST_BUS_MMC1 3 > +#define RST_BUS_DRAM 4 > +#define RST_BUS_SPI0 5 > +#define RST_BUS_SPI1 6 > +#define RST_BUS_OTG 7 > +#define RST_BUS_VE 8 > +#define RST_BUS_LCD 9 > +#define RST_BUS_DEINTERLACE 10 > +#define RST_BUS_CSI 11 > +#define RST_BUS_TVD 12 > +#define RST_BUS_TVE 13 > +#define RST_BUS_DE_BE 14 > +#define RST_BUS_DE_FE 15 > +#define RST_BUS_CODEC 16 > +#define RST_BUS_SPDIF 17 > +#define RST_BUS_IR 18 > +#define RST_BUS_RSB 19 > +#define RST_BUS_I2S0 20 > +#define RST_BUS_I2C0 21 > +#define RST_BUS_I2C1 22 > +#define RST_BUS_I2C2 23 > +#define RST_BUS_UART0 24 > +#define RST_BUS_UART1 25 > +#define RST_BUS_UART2 26 > + > +#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */