[PATCH v2] imx8m: clock_imx8mq: Add the ecspi clocks

[Angus Ainslie]

Enable the clocks for spi buses 1 through 3

Signed-off-by: Angus Ainslie <an...@akkea.ca>
---

Changes since v1:

added MXC_CSPI_CLK to ECSPI1_CLK_ROOT mapping

 arch/arm/include/asm/arch-imx8m/imx-regs.h |  9 +++++
 arch/arm/mach-imx/imx8m/clock_imx8mq.c     | 40 ++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1..8cb499d3a3 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -94,6 +94,15 @@
 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
 #define SRC_DDR1_RCR_PRESET_N_MASK     BIT(0)
 
+#define IMX_CSPI1_BASE         0x30820000
+#define IMX_CSPI2_BASE         0x30830000
+#define IMX_CSPI3_BASE         0x30840000
+
+#define MXC_SPI_BASE_ADDRESSES \
+       IMX_CSPI1_BASE, \
+       IMX_CSPI2_BASE, \
+       IMX_CSPI3_BASE
+
 struct iomuxc_gpr_base_regs {
        u32 gpr[47];
 };
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 60e2218a3c..ef0249cd58 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -359,6 +359,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                clock_get_target_val(IPG_CLK_ROOT, &val);
                val = val & 0x3;
                return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+       case MXC_CSPI_CLK:
+               return get_root_clk(ECSPI1_CLK_ROOT);
        case MXC_ESDHC_CLK:
                return get_root_clk(USDHC1_CLK_ROOT);
        case MXC_ESDHC2_CLK:
@@ -505,6 +507,31 @@ int set_clk_qspi(void)
        return 0;
 }
 
+int set_clk_ecspi(int sel)
+{
+       int clk = ECSPI1_CLK_ROOT;
+
+       switch (sel) {
+       case 1:
+               clk = ECSPI1_CLK_ROOT;
+               break;
+       case 2:
+               clk = ECSPI2_CLK_ROOT;
+               break;
+       case 3:
+               clk = ECSPI3_CLK_ROOT;
+               break;
+       }
+
+       clock_enable(clk, 0);
+       /*
+        * TODO: configure clock
+        */
+       clock_enable(clk, 1);
+
+       return 0;
+}
+
 #ifdef CONFIG_FEC_MXC
 int set_clk_enet(enum enet_freq type)
 {
@@ -772,6 +799,19 @@ int clock_init(void)
        clock_enable(CCGR_TSENSOR, 1);
        clock_enable(CCGR_OCOTP, 1);
 
+       /*
+        * set ecspi roots
+        */
+       clock_enable(CCGR_ECSPI1, 0);
+       clock_enable(CCGR_ECSPI2, 0);
+       clock_enable(CCGR_ECSPI3, 0);
+       clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(0));
+       clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(0));
+       clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | 
CLK_ROOT_SOURCE_SEL(0));
+       clock_enable(CCGR_ECSPI1, 1);
+       clock_enable(CCGR_ECSPI2, 1);
+       clock_enable(CCGR_ECSPI3, 1);
+
        /* config GIC ROOT to sys_pll2_200m */
        clock_enable(CCGR_GIC, 0);
        clock_set_target_val(GIC_CLK_ROOT,
-- 
2.25.1