The patch supports setting the "CONT" bit of the configuration
register and adding a continuous read mode flag for identification.
Signed-off-by: Zhengxun <zhengxunli.m...@gmail.com>
---
drivers/mtd/nand/spi/core.c | 11 +++++++++++
include/linux/mtd/spinand.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index e5330958c7..88d07b625d 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -216,6 +216,17 @@ static int spinand_init_quad_enable(struct spinand_device
*spinand)
enable ? CFG_QUAD_ENABLE : 0);
}
+static int spinand_continuous_read_enable(struct spinand_device *spinand)
+{
+ return spinand_upd_cfg(spinand, CFG_CONT_READ_ENABLE,
+ CFG_CONT_READ_ENABLE);
+}
+
+static int spinand_continuous_read_disable(struct spinand_device *spinand)
+{
+ return spinand_upd_cfg(spinand, CFG_CONT_READ_ENABLE, 0);
+}
+
static int spinand_ecc_enable(struct spinand_device *spinand,
bool enable)
{
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 15bcd59f34..e6a5478b0a 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -131,6 +131,7 @@
#define REG_CFG 0xb0
#define CFG_OTP_ENABLE BIT(6)
#define CFG_ECC_ENABLE BIT(4)
+#define CFG_CONT_READ_ENABLE BIT(2)
#define CFG_QUAD_ENABLE BIT(0)
/* status register */
@@ -247,6 +248,7 @@ struct spinand_ecc_info {
#define SPINAND_HAS_QE_BIT BIT(0)
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
+#define SPINAND_HAS_CONT_READ_BIT BIT(2)
/**
* struct spinand_info - Structure used to describe SPI NAND chips
--
2.17.1
