On Tue, 30 Nov 2010 22:25:11 +0100 Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote:
> Scott Wood <scottw...@freescale.com> wrote on 2010/11/30 22:17:31: > > > > On Tue, 30 Nov 2010 22:13:32 +0100 > > Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote: > > > > > Scott Wood <scottw...@freescale.com> wrote on 2010/11/30 21:50:52: > > > > > > > > On Tue, 30 Nov 2010 21:45:19 +0100 > > > > Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote: > > > > > > > > > On a related note, I am not sure why the I and D cache needs to be > > > > > flushed, > > > > > aren't they coherent? > > > > > > > > They are not. > > > > > > Ah, I figured they would be these days. > > > > Nope, I've seen weird stuff happen when I forget to sync the icache > > even on very recent chips (albeit 85xx and not 83xx). > > > > > I doubt one needs to invalidate the icache though? > > > Better safe than sorry I guess, one could probably optimize it a > > > little bit though. > > > > You need to flush the dcache and then invalidate the icache. > > but if one haven't executed any insn's at the new location yet > there should not be any cache lines in the icache that > match the new location. Ah. That's a special case. :-) Still, better to set a good example. -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
