po 14. 3. 2022 v 15:26 odesÃlatel Michal Simek <michal.si...@xilinx.com> napsal: > > Production SOM has emmc on it and make sense to describe pin description to > be able use EMMC if it is not configured via psu_init. > (Still some regs are not handled but this is one step in that direction) > > Signed-off-by: Michal Simek <michal.si...@xilinx.com> > --- > > arch/arm/dts/zynqmp-sm-k26-revA.dts | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts > b/arch/arm/dts/zynqmp-sm-k26-revA.dts > index b437d713ca8f..e904cd8ea093 100644 > --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts > +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts > @@ -14,6 +14,7 @@ > #include <dt-bindings/input/input.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> > > / { > model = "ZynqMP SM-K26 Rev1/B/A"; > @@ -92,6 +93,23 @@ > status = "okay"; > }; > > +&pinctrl0 { > + status = "okay"; > + pinctrl_sdhci0_default: sdhci0-default { > + conf { > + groups = "sdio0_0_grp"; > + slew-rate = <SLEW_RATE_SLOW>; > + power-source = <IO_STANDARD_LVCMOS18>; > + bias-disable; > + }; > + > + mux { > + groups = "sdio0_0_grp"; > + function = "sdio0"; > + }; > + }; > +}; > + > &qspi { /* MIO 0-5 - U143 */ > status = "okay"; > flash@0 { /* MT25QU512A */ > @@ -185,6 +203,8 @@ > > &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ > status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sdhci0_default>; > non-removable; > disable-wp; > bus-width = <8>; > -- > 2.35.1 >
Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs