Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.
Signed-off-by: Dave Gerlach <d-gerl...@ti.com>
---
.../memory-controller/k3-j721e-ddrss.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index dd0260b39407..df3290a6b9d9 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -13,6 +13,7 @@ Required properties:
"ti,am64-ddrss" for am642
- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
+ ss - Map the DDRSS configuration region
- reg: Contains the register map per reg-names.
- power-domains: Should contain two entries:
- an entry to TISCI DDR CFG device
@@ -32,6 +33,13 @@ Required properties:
- ti,pi-data: An array containing the phy independent block settings
- ti,phy-data: An array containing the ddr phy settings.
+Optional properties:
+--------------------
+- reg-names ss - Map the DDRSS configuration region
+- reg: Must add "ss" to list if the above ss region is
included.
+- ti,ecc-enable: Boolean flag to enable ECC. This will reduce available
DDR
+ by 1/9.
+
Example (J721E):
================
--
2.35.0
