Sorry for the two successive posts, I looked at the disassembly... On Wed, Dec 1, 2010 at 1:26 AM, 奥刘 <happyo...@gmail.com> wrote: > Dear All: > > Recently , i have build a embedded environment with Uboot . And My Chip > is adm5120 , mips4kc code. > > In the file .\cpu\mips\cache.s , i found some code confounded . > > line 152 to line 156 : > > cache_op Index_Store_Tag_I t0 > PTR_ADDU t0, a2 > bne t0, t1, 1b > /* fill once, so data field parity is correct */ > PTR_LI t0, INDEX_BASE > > the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this > instruction will be implement every branch cycle. > > Is it right ? Then the cache operation logic seems wrong .
The assembler does insert a 'NOP' instruction in the branch delay slot, even with ".set noreorder", so this is OK: 810005a8: bd140000 cache 0x14,0(t0) 810005ac: 01064021 addu t0,t0,a2 810005b0: 1509fffd bne t0,t1,810005a8 <mips_init_icache+0x28> 810005b4: 00000000 nop -- Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot