On Thu, 17 Mar 2022 23:52:36 -0500
Samuel Holland <sam...@sholland.org> wrote:
> Currently, clock/reset setup for this device is handled by a
> platform-specific function and is intermixed with non-DM pinctrl
> setup. Use the devicetree to get clocks/resets, which disentagles
> it from the pinctrl setup in preparation for moving to DM_PINCTRL.
>
> This also has the added benefit of picking the right clock/reset
> bits for H6 and new SoCs that have a rearranged PRCM MMIO space.
So does this actually work right now with the A23/A33? They have specific
clocks for the RSB gates/resets, and I don't see support for that in the
tree right now? Or this is just fine because those clocks are treated
optional and their enabling is actually redundant, in practice?
Cheers,
Andre
>
> Signed-off-by: Samuel Holland <sam...@sholland.org>
> ---
>
> drivers/i2c/sun8i_rsb.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
> index 0681e398f7..e3a44e6a1b 100644
> --- a/drivers/i2c/sun8i_rsb.c
> +++ b/drivers/i2c/sun8i_rsb.c
> @@ -9,10 +9,12 @@
> */
>
> #include <axp_pmic.h>
> +#include <clk.h>
> #include <common.h>
> #include <dm.h>
> #include <errno.h>
> #include <i2c.h>
> +#include <reset.h>
> #include <time.h>
> #include <asm/arch/cpu.h>
> #include <asm/arch/gpio.h>
> @@ -243,9 +245,19 @@ static int sun8i_rsb_probe_chip(struct udevice *bus,
> uint chip_addr,
> static int sun8i_rsb_probe(struct udevice *bus)
> {
> struct sun8i_rsb_priv *priv = dev_get_priv(bus);
> + struct reset_ctl *reset;
> + struct clk *clk;
>
> priv->base = dev_read_addr_ptr(bus);
>
> + reset = devm_reset_control_get(bus, NULL);
> + if (!IS_ERR(reset))
> + reset_deassert(reset);
> +
> + clk = devm_clk_get(bus, NULL);
> + if (!IS_ERR(clk))
> + clk_enable(clk);
> +
> return sun8i_rsb_init(priv->base);
> }
>
