> The current DDR write level calibration routine always overwrite > the ralat/walat fields to their maximum value, just save > the existing values at the beginning of the calibration routine > and restore it at the end. > In case the delay is estimated by the user to be more than one cycle the > walat should be configured according to that, this is not > automatically done. From the i.MX6 RM: > The user should read the results of the associated delay-line at > MPWLDECTRL#[WL_DL_ABS_OFFSET#] and in case the user estimates that the > reasonable delay may be above 1 cycle then the user should indicate it at > MPWLDECTRL#[WL_CYC_DEL#]. Moreover the user should indicate it in > MDMISC[WALAT] field. For example, if the result of the write leveling > calibration > is 100/256 parts of a cycle, but the user estimates that the delay is > above 2 cycles > then MPWLDECTRL#[WL_CYC_DEL#] should be configured to 2, so the total > delay will be 2 and 100/256 parts of a cycle > Probably it would just possible to not overwrite the mdmisc register in > the first place, since this is not present in the write_level_calib() example > in NXP AN4467 nor in the i.MX6 RM (44.11.6.1 Hardware Write Leveling > Calibration). > Fixes: d339f16911c7 ("arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL") > Signed-off-by: Francesco Dolcini <francesco.dolc...@toradex.com> > Reviewed-by: Marek Vasut <ma...@denx.de> > Reviewed-by: Fabio Estevam <feste...@denx.de> Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =====================================================================