[PATCH v11 04/16] rockchip: rk3066: add rk3066 pinctrl driver

[Johan Jonker]

From: Paweł Jarosz <paweljarosz3...@gmail.com>

Add driver supporting pin multiplexing on rk3066 platform.

Signed-off-by: Paweł Jarosz <paweljarosz3...@gmail.com>
Signed-off-by: Johan Jonker <jbx6...@gmail.com>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
---

Changed V9:
  change regmap source

Changed V7:
  restyle
  changed function prefix.
  restyle U_BOOT_DRIVER structure
  use OF_REAL
  use EOPNOTSUPP
---
 drivers/pinctrl/rockchip/Makefile         |   1 +
 drivers/pinctrl/rockchip/pinctrl-rk3066.c | 112 ++++++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3066.c

diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index fcf19f877a..7d03f8101d 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -5,6 +5,7 @@
 obj-y += pinctrl-rockchip-core.o
 obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o
 obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c 
b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
new file mode 100644
index 0000000000..598b63223e
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-rockchip.h"
+
+static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int 
mux)
+{
+       struct rockchip_pinctrl_priv *priv = bank->priv;
+       int iomux_num = (pin / 8);
+       struct regmap *regmap;
+       int reg, ret, mask, mux_type;
+       u8 bit;
+       u32 data;
+
+       regmap = priv->regmap_base;
+
+       /* get basic quadrupel of mux registers and the correct reg inside */
+       mux_type = bank->iomux[iomux_num].type;
+       reg = bank->iomux[iomux_num].offset;
+       reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
+
+       data = (mask << (bit + 16));
+       data |= (mux & mask) << bit;
+       ret = regmap_write(regmap, reg, data);
+
+       return ret;
+}
+
+#define RK3066_PULL_OFFSET             0x118
+#define RK3066_PULL_PINS_PER_REG       16
+#define RK3066_PULL_BANK_STRIDE                8
+
+static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank 
*bank,
+                                                int pin_num, struct regmap 
**regmap,
+                                                int *reg, u8 *bit)
+{
+       struct rockchip_pinctrl_priv *priv = bank->priv;
+
+       *regmap = priv->regmap_base;
+       *reg = RK3066_PULL_OFFSET;
+       *reg += bank->bank_num * RK3066_PULL_BANK_STRIDE;
+       *reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4;
+
+       *bit = pin_num % RK3066_PULL_PINS_PER_REG;
+};
+
+static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank,
+                                  int pin_num, int pull)
+{
+       struct regmap *regmap;
+       int reg, ret;
+       u8 bit;
+       u32 data;
+
+       if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
+           pull != PIN_CONFIG_BIAS_DISABLE)
+               return -EOPNOTSUPP;
+
+       rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, 
&bit);
+       data = BIT(bit + 16);
+       if (pull == PIN_CONFIG_BIAS_DISABLE)
+               data |= BIT(bit);
+       ret = regmap_write(regmap, reg, data);
+
+       return ret;
+}
+
+static struct rockchip_pin_bank rk3066_pin_banks[] = {
+       PIN_BANK(0, 32, "gpio0"),
+       PIN_BANK(1, 32, "gpio1"),
+       PIN_BANK(2, 32, "gpio2"),
+       PIN_BANK(3, 32, "gpio3"),
+       PIN_BANK(4, 32, "gpio4"),
+       PIN_BANK(6, 16, "gpio6"),
+};
+
+static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
+       .pin_banks              = rk3066_pin_banks,
+       .nr_banks               = ARRAY_SIZE(rk3066_pin_banks),
+       .grf_mux_offset         = 0xa8,
+       .set_mux                = rk3066_pinctrl_set_mux,
+       .set_pull               = rk3066_pinctrl_set_pull,
+};
+
+static const struct udevice_id rk3066_pinctrl_ids[] = {
+       {
+               .compatible = "rockchip,rk3066a-pinctrl",
+               .data = (ulong)&rk3066_pin_ctrl
+       },
+       {}
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
+       .name           = "rockchip_rk3066a_pinctrl",
+       .id             = UCLASS_PINCTRL,
+       .ops            = &rockchip_pinctrl_ops,
+       .probe          = rockchip_pinctrl_probe,
+#if CONFIG_IS_ENABLED(OF_REAL)
+       .bind           = dm_scan_fdt_dev,
+#endif
+       .of_match       = rk3066_pinctrl_ids,
+       .priv_auto      = sizeof(struct rockchip_pinctrl_priv),
+};
-- 
2.20.1