On Thu, Apr 21, 2022 at 08:09:59PM -0400, Sean Anderson wrote: > On 4/21/22 2:48 AM, Tommaso Merciai wrote: > > Hi, > > I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF > > clocks. After port all necessary clocks needed by eLCDIF I found that > > IMX8MM_VIDEO_PLL1 clock is not enabled and need the following code to enable > > it at the end of the clk-imx8mm probe: > > > > struct clk *clkp; > > > > clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); > > clk_set_rate(clkp, 594000000UL); > > clk_enable(clkp); > > > > What do you think about this solution? > > There is a more standard way to do this? > > PLL1 should be a parent of one of the clocks required by the eLCDIF. That > clock > should call clk_enable() on PLL1 when it is enabled itself. If you want to set > a specific rate, you can do that with assigned-clock-rates in either the > clock's > DT node, or the eLCDIF's DT node.
Hi Sean, Thanks for your suggestion, I need only to enable it, I have already assign the right rate from dts. The doubt at this point is: it's right call clk_enable from clk-imx8mm.c? I think yes because it handle by "fsl,imx8mm-ccm" driver, maybe protected by CONFIG_DM_VIDEO could be a good solution. Let me know. Thanks, Tommaso > > --Sean -- Tommaso Merciai Embedded Linux Engineer tommaso.merc...@amarulasolutions.com __________________________________ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 i...@amarulasolutions.com www.amarulasolutions.com