CZ.NIC Turris 1.0 and 1.1 are open source routers, they have dual-core PowerPC Freescale P2020 CPU and are based on Freescale P2020RDB-PC-A board.
Hardware design is fully open source, all firmware and hardware design files are available at Turris project website: https://docs.turris.cz/hw/turris-1x/turris-1x/ https://project.turris.cz/en/hardware.html This patch adds full U-Boot support for CZ.NIC Turris 1.x routers. P2020 BootROM can load U-Boot either from NOR flash or from SD card. So there is defconfig file turris_1x_nor_defconfig which builds NOR version and defconfig file turris_1x_sdcard_defconfig which builds SD card version. Design of CZ.NIC Turris 1.x routers is based on Freescale P2020RDB-PC-A board, so common board code from boards/freescale/p1_p2_rdb_pc directory is shared and linked also into Turris 1.x U-Boot board code. Turris 1.x code in this patch uses modern distroboot and can boot Linux kernel from various locations, including NAND, SD card, USB flash disks, NVMe disks or SATA disks (connected to extra SATA/SCSI PCIe controllers). Signed-off-by: Pali Rohár <p...@kernel.org> --- This patch depends on other powerpc patches: https://patchwork.ozlabs.org/bundle/pali/powerpc/ --- arch/powerpc/cpu/mpc85xx/Kconfig | 6 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/turris1x-u-boot.dtsi | 13 + arch/powerpc/dts/turris1x.dts | 475 ++++++++++++++++++++++++++ board/CZ.NIC/turris_1x/Kconfig | 177 ++++++++++ board/CZ.NIC/turris_1x/MAINTAINERS | 11 + board/CZ.NIC/turris_1x/Makefile | 15 + board/CZ.NIC/turris_1x/ddr.c | 27 ++ board/CZ.NIC/turris_1x/law.c | 13 + board/CZ.NIC/turris_1x/lbc.c | 26 ++ board/CZ.NIC/turris_1x/tlb.c | 142 ++++++++ board/CZ.NIC/turris_1x/turris_1x.c | 106 ++++++ configs/turris_1x_nor_defconfig | 50 +++ configs/turris_1x_sdcard_defconfig | 66 ++++ include/configs/turris_1x.h | 381 +++++++++++++++++++++ 15 files changed, 1509 insertions(+) create mode 100644 arch/powerpc/dts/turris1x-u-boot.dtsi create mode 100644 arch/powerpc/dts/turris1x.dts create mode 100644 board/CZ.NIC/turris_1x/Kconfig create mode 100644 board/CZ.NIC/turris_1x/MAINTAINERS create mode 100644 board/CZ.NIC/turris_1x/Makefile create mode 100644 board/CZ.NIC/turris_1x/ddr.c create mode 100644 board/CZ.NIC/turris_1x/law.c create mode 100644 board/CZ.NIC/turris_1x/lbc.c create mode 100644 board/CZ.NIC/turris_1x/tlb.c create mode 100644 board/CZ.NIC/turris_1x/turris_1x.c create mode 100644 configs/turris_1x_nor_defconfig create mode 100644 configs/turris_1x_sdcard_defconfig create mode 100644 include/configs/turris_1x.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 6f8b7593d250..28f69e7c73d2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -150,6 +150,11 @@ config TARGET_P2020RDB imply CMD_SATA imply SATA_SIL +config TARGET_TURRIS_1X + bool "Support Turris 1.x" + select SUPPORT_SPL + select ARCH_P2020 + config TARGET_P2041RDB bool "Support P2041RDB" select ARCH_P2041 @@ -1201,6 +1206,7 @@ config SYS_FSL_LBC_CLK_DIV config FSL_VIA bool +source "board/CZ.NIC/turris_1x/Kconfig" source "board/emulation/qemu-ppce500/Kconfig" source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index a4b0d7ddc4ff..d6462101211e 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb +dtb-$(CONFIG_TARGET_TURRIS_1X) += turris1x.dtb dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb diff --git a/arch/powerpc/dts/turris1x-u-boot.dtsi b/arch/powerpc/dts/turris1x-u-boot.dtsi new file mode 100644 index 000000000000..aa758818d564 --- /dev/null +++ b/arch/powerpc/dts/turris1x-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&soc { + i2c@3000 { + u-boot,dm-pre-reloc; + + crypto@64 { + u-boot,dm-pre-reloc; + }; + }; +}; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/turris1x.dts b/arch/powerpc/dts/turris1x.dts new file mode 100644 index 000000000000..1b27c1b0bba6 --- /dev/null +++ b/arch/powerpc/dts/turris1x.dts @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Turris 1.x Device Tree Source + * + * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/) + * + * Pinout, Schematics and Altium hardware design files are open source + * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +/include/ "fsl/p2020si-pre.dtsi" + +/ { + model = "Turris 1.x"; + compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */ + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + }; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x00100000>; + + i2c@3000 { + /* PCA9557PW GPIO controller for boot config */ + gpio-controller@18 { + compatible = "nxp,pca9557"; + label = "bootcfg"; + reg = <0x18>; + #gpio-cells = <2>; + gpio-controller; + polarity = <0x00>; + }; + + /* STM32F030R8T6 MCU for power control */ + power-control@2a { + /* + * Turris Power Control firmware runs on STM32F0 MCU. + * This firmware is open source and available at: + * https://gitlab.nic.cz/turris/hw/turris_power_control + */ + reg = <0x2a>; + }; + + /* DDR3 SPD/EEPROM PSWP instruction */ + eeprom@32 { + reg = <0x32>; + }; + + /* SA56004ED temperature control */ + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */ + <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */ + }; + + /* DDR3 SPD/EEPROM */ + eeprom@52 { + compatible = "atmel,spd"; + reg = <0x52>; + }; + + /* MCP79402-I/ST Protected EEPROM */ + eeprom@57 { + reg = <0x57>; + }; + + /* ATSHA204-TH-DA-T crypto module */ + crypto@64 { + compatible = "atmel,atsha204"; + reg = <0x64>; + }; + + /* IDT6V49205BNLGI clock generator */ + clock-generator@69 { + compatible = "idt,6v49205b"; + reg = <0x69>; + }; + + /* MCP79402-I/ST RTC */ + rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + interrupt-parent = <&gpio>; + interrupts = <14 0>; /* GPIO14 - MFP pin */ + }; + }; + + /* SPI on connector P1 */ + spi0: spi@7000 { + }; + + gpio: gpio-controller@fc00 { + #interrupt-cells = <2>; + interrupt-controller; + }; + + /* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */ + usb@22000 { + phy_type = "ulpi"; + dr_mode = "host"; + }; + + enet0: ethernet@24000 { + /* Connected to port 6 of QCA8337N-AL3C switch */ + phy-connection-type = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio@24520 { + /* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */ + switch@10 { + compatible = "qca,qca8337"; + interrupts = <2 1 0 0>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu1"; + ethernet = <&enet1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "lan5"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan2"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + }; + + port@6 { + reg = <6>; + label = "cpu0"; + ethernet = <&enet0>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + /* KSZ9031RNXCA ethernet phy for WAN port */ + phy: ethernet-phy@7 { + interrupts = <3 1 0 0>; + reg = <0x7>; + }; + }; + + ptp_clock@24e00 { + fsl,tclk-period = <5>; + fsl,tmr-prsc = <200>; + fsl,tmr-add = <0xcccccccd>; + fsl,tmr-fiper1 = <0x3b9ac9fb>; + fsl,tmr-fiper2 = <0x0001869b>; + fsl,max-adj = <249999999>; + }; + + enet1: ethernet@25000 { + /* Connected to port 0 of QCA8337N-AL3C switch */ + phy-connection-type = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio@25520 { + status = "disabled"; + }; + + enet2: ethernet@26000 { + /* Connected to KSZ9031RNXCA ethernet phy (WAN port) */ + label = "wan"; + phy-handle = <&phy>; + phy-connection-type = "rgmii-id"; + }; + + mdio@26520 { + status = "disabled"; + }; + + sdhc@2e000 { + bus-width = <4>; + cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + }; + + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + + ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */ + <0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */ + <0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */ + + /* S29GL128P90TFIR10 NOR */ + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x0 0x01000000>; + bank-width = <2>; + device-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + /* 128 kB for Device Tree Blob */ + reg = <0x00000000 0x00020000>; + label = "dtb"; + }; + + partition@20000 { + /* 1.7 MB for Rescue Linux Kernel Image */ + reg = <0x00020000 0x001a0000>; + label = "rescue-kernel"; + }; + + partition@1c0000 { + /* 1.5 MB for Rescue JFFS2 Root File System */ + reg = <0x001c0000 0x00180000>; + label = "rescue-rootfs"; + }; + + partition@340000 { + /* 11 MB for TAR.XZ Backup with content of NAND Root File System */ + reg = <0x00340000 0x00b00000>; + label = "backup-rootfs"; + }; + + partition@e40000 { + /* 768 kB for Certificates JFFS2 File System */ + reg = <0x00e40000 0x000c0000>; + label = "certificates"; + }; + + /* free unused space 0x00f00000-0x00f20000 */ + + partition@f20000 { + /* 128 kB for U-Boot Environment Variables */ + reg = <0x00f20000 0x00020000>; + label = "u-boot-env"; + }; + + partition@f40000 { + /* 768 kB for U-Boot Bootloader Image */ + reg = <0x00f40000 0x000c0000>; + label = "u-boot"; + }; + }; + }; + + /* MT29F2G08ABAEAWP:E NAND */ + nand@1,0 { + compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand"; + reg = <0x1 0x0 0x00040000>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "bch"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + /* 256 MB for UBI with one volume: UBIFS Root File System */ + reg = <0x00000000 0x10000000>; + label = "rootfs"; + }; + }; + }; + + /* LCMXO1200C-3FTN256C FPGA */ + cpld@3,0 { + /* + * Turris CPLD firmware which runs on this Lattice FPGA, + * is extended version of P1021RDB-PC CPLD v4.1 firmware. + * It is backward compatible with its original version + * and the only extension is support for Turris LEDs. + * Turris CPLD firmware is open source and available at: + * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v + */ + compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus"; + reg = <0x3 0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3 0x0 0x00020000>; + + /* MAX6370KA+T watchdog */ + watchdog@2 { + /* + * CPLD firmware maps SET0, SET1 and SET2 + * input logic of MAX6370KA+T chip to CPLD + * memory space at byte offset 0x2. WDI + * input logic is outside of the CPLD and + * connected via external GPIO. + */ + compatible = "maxim,max6370"; + reg = <0x02 0x01>; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + led-controller@13 { + /* + * LEDs are controlled by CPLD firmware. + * All five LAN LEDs share common RGB settings + * and so it is not possible to set different + * colors on different LAN ports. + */ + compatible = "cznic,turris1x-leds"; + reg = <0x13 0x1d>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + reg = <0x0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_WAN; + }; + + multi-led@1 { + reg = <0x1>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <5>; + }; + + multi-led@2 { + reg = <0x2>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + }; + + multi-led@3 { + reg = <0x3>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + }; + + multi-led@4 { + reg = <0x4>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + }; + + multi-led@5 { + reg = <0x5>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + + multi-led@6 { + reg = <0x6>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_WLAN; + }; + + multi-led@7 { + reg = <0x7>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_POWER; + }; + }; + }; + }; + + pci2: pcie@ffe08000 { + /* + * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller. + * This xHCI controller is available only on Turris 1.1 boards. + * Turris 1.0 boards have nothing connected to this PCIe bus, + * so system would see only PCIe Root Port of this PCIe Root + * Complex. TUSB7340RKM xHCI controller has four SuperSpeed + * channels. Channel 0 is connected to the front USB 3.0 port, + * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe + * slot 1 (CN5), channels 2 and 3 to connector P600. + * + * P2020 PCIe Root Port uses 1MB of PCIe MEM and xHCI controller + * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required. + * So allocate 2MB of PCIe MEM for this PCIe bus. + */ + reg = <0 0xffe08000 0 0x1000>; + ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00200000>, /* MEM */ + <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */ + + pcie@0 { + ranges; + }; + }; + + pci1: pcie@ffe09000 { + /* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */ + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */ + <0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */ + + pcie@0 { + ranges; + }; + }; + + pci0: pcie@ffe0a000 { + /* + * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card. + * Turris 1.1 boards have in this mPCIe slot additional USB 2.0 + * pins via channel 1 of TUSB7340RKM xHCI controller and also + * additional SIM card slot, both for USB-based WWAN cards. + */ + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */ + <0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */ + + pcie@0 { + ranges; + }; + }; +}; + +/include/ "fsl/p2020si-post.dtsi" diff --git a/board/CZ.NIC/turris_1x/Kconfig b/board/CZ.NIC/turris_1x/Kconfig new file mode 100644 index 000000000000..103c00d585d7 --- /dev/null +++ b/board/CZ.NIC/turris_1x/Kconfig @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) 2022 Pali Rohár <p...@kernel.org> + +if TARGET_TURRIS_1X + +# Board identification +config SYS_BOARD + default "turris_1x" +config SYS_VENDOR + default "CZ.NIC" +config SYS_CONFIG_NAME + default "turris_1x" +config DEFAULT_DEVICE_TREE + default "turris1x" + +# Board functions +config ATSHA204A + default y +config BOARD_EARLY_INIT_F + default y +config BOARD_EARLY_INIT_R + default y +config LAST_STAGE_INIT + default y +config OF_BOARD_SETUP + default y +config MISC + default y + +# ENV +config ENV_SIZE + default 0x2000 +config ENV_SECT_SIZE + default 0x20000 +config ENV_OVERWRITE + default y +config ENV_IS_IN_FLASH + default y +config ENV_ADDR + default 0xeff20000 # in NOR +config SYS_RELOC_GD_ENV_ADDR + default y + +# DDR +config DDR_CLK_FREQ + default 66666666 + +# UART +config DEBUG_UART_BASE + default 0xffe04500 if DEBUG_UART +config DEBUG_UART_CLOCK + default 37500000 if DEBUG_UART +config SYS_NS16550 + default y + +# I2C +config I2C_SET_DEFAULT_BUS_NUM + default y +config SYS_FSL_I2C_OFFSET + default 0x3000 +config SYS_FSL_HAS_I2C2_OFFSET + default y +config SYS_FSL_I2C2_OFFSET + default 0x3100 +config SYS_I2C_FSL + default y + +# PCIe +config PCI_INIT_R + default y +config PCIE_FSL + default y + +# Ethernet +config MII + default y +config PHY_FIXED + default y +config TSEC_ENET + default y + +# USB +config USB_EHCI_FSL + default y +config USB_XHCI_HCD + default y +config USB_XHCI_PCI + default y + +# SDHC +config FSL_ESDHC + default y +config FSL_PREPBL_ESDHC_BOOT_SECTOR + default y if SYS_EXTRA_OPTIONS = SDCARD +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH + default 4 + +# NOR (CS0) +config SYS_BR0_PRELIM_BOOL + default y +config SYS_BR0_PRELIM + default 0xef001001 # (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_MS_GPCM | BR_V) +config SYS_OR0_PRELIM + default 0xff000ff7 # (OR_AM_16MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +config MTD_NOR_FLASH + default y +config CFI_FLASH + default y +config FLASH_CFI_MTD + default y +config SYS_FLASH_USE_BUFFER_WRITE + default y + +# NAND (CS1) +config SYS_BR1_PRELIM_BOOL + default y +config SYS_BR1_PRELIM + default 0xff800821 # (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) | BR_PS_8 | BR_MS_FCM | BR_V) +config SYS_OR1_PRELIM + default 0xfffc0796 # (OR_AM_256KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) +config MTD_RAW_NAND + default y +config NAND_FSL_ELBC + default y +config NAND_FSL_ELBC_DT + default y +config BCH + default y +config SYS_FLASH_CFI + default y + +# CPLD (CS3) +config SYS_BR3_PRELIM_BOOL + default y +config SYS_BR3_PRELIM + default 0xffa00801 # (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | BR_PS_8 | BR_MS_GPCM | BR_V) +config SYS_OR3_PRELIM + default 0xfffe09f7 # (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +config MPC85XX_HAVE_RESET_VECTOR + default y if SYS_EXTRA_OPTIONS != SDCARD + +config SYS_TEXT_BASE + default 0x11000000 if SPL # in DDR + default 0xf8f80000 if SYS_EXTRA_OPTIONS = SDCARD # in SRAM + default 0xeff40000 # in NOR + +if SPL + +config SPL_TEXT_BASE + default 0xf8f80000 if SYS_EXTRA_OPTIONS = SDCARD # in SRAM + default 0xeff40000 # in NOR + +config SPL_ENV_SUPPORT + default y +config SPL_FRAMEWORK + default n +config SPL_I2C + default y +config SPL_LIBCOMMON_SUPPORT + default y +config SPL_LIBGENERIC_SUPPORT + default y +config SPL_MMC + default y if SYS_EXTRA_OPTIONS = SDCARD +config SPL_MMC_BOOT + default y if SYS_EXTRA_OPTIONS = SDCARD +config SPL_MPC8XXX_INIT_DDR + default y +config SPL_SERIAL + default y +config SPL_SYS_I2C_LEGACY + default y + +endif + +endif diff --git a/board/CZ.NIC/turris_1x/MAINTAINERS b/board/CZ.NIC/turris_1x/MAINTAINERS new file mode 100644 index 000000000000..04f4915f7d7d --- /dev/null +++ b/board/CZ.NIC/turris_1x/MAINTAINERS @@ -0,0 +1,11 @@ +TURRIS 1.X BOARD +M: Pali Rohár <p...@kernel.org> +S: Maintained +F: arch/powerpc/dts/turris1x-u-boot.dtsi +F: arch/powerpc/dts/turris1x.dts +F: board/CZ.NIC/turris_1x/ +F: board/CZ.NIC/turris_atsha_otp.c +F: board/CZ.NIC/turris_atsha_otp.h +F: configs/turris_1x_nor_defconfig +F: configs/turris_1x_sdcard_defconfig +F: include/configs/turris_1x.h diff --git a/board/CZ.NIC/turris_1x/Makefile b/board/CZ.NIC/turris_1x/Makefile new file mode 100644 index 000000000000..d935456d27c9 --- /dev/null +++ b/board/CZ.NIC/turris_1x/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) 2022 Pali Rohár <p...@kernel.org> + +ifdef CONFIG_SPL_BUILD +obj-y += ../../freescale/p1_p2_rdb_pc/spl.o +endif + +obj-y += ../../freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.o +obj-y += ../turris_atsha_otp.o + +obj-y += turris_1x.o +obj-y += ddr.o +obj-y += law.o +obj-y += lbc.o +obj-y += tlb.o diff --git a/board/CZ.NIC/turris_1x/ddr.c b/board/CZ.NIC/turris_1x/ddr.c new file mode 100644 index 000000000000..ced4e97bfa30 --- /dev/null +++ b/board/CZ.NIC/turris_1x/ddr.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <p...@kernel.org> + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) +{ + int i; + + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/CZ.NIC/turris_1x/law.c b/board/CZ.NIC/turris_1x/law.c new file mode 100644 index 000000000000..1502ceecf823 --- /dev/null +++ b/board/CZ.NIC/turris_1x/law.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <p...@kernel.org> + +#include <common.h> +#include <asm/fsl_law.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/CZ.NIC/turris_1x/lbc.c b/board/CZ.NIC/turris_1x/lbc.c new file mode 100644 index 000000000000..de2f5d25da6d --- /dev/null +++ b/board/CZ.NIC/turris_1x/lbc.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <p...@kernel.org> + +#include <common.h> +#include <asm/fsl_lbc.h> +#include <linux/build_bug.h> + +/* + * Check if preliminary base/options config options have correct values. + * Due to broken build system, it is not possible to define these options + * in config.h file nor in other sane place. So do compile time checks here. + */ + +#define LBC_BR_NOR (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_MS_GPCM | BR_V) +#define LBC_OR_NOR (OR_AM_16MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define LBC_BR_NAND (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) | BR_PS_8 | BR_MS_FCM | BR_V) +#define LBC_OR_NAND (OR_AM_256KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) +#define LBC_BR_CPLD (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | BR_PS_8 | BR_MS_GPCM | BR_V) +#define LBC_OR_CPLD (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +static_assert(CONFIG_SYS_BR0_PRELIM == LBC_BR_NOR); +static_assert(CONFIG_SYS_OR0_PRELIM == LBC_OR_NOR); +static_assert(CONFIG_SYS_BR1_PRELIM == LBC_BR_NAND); +static_assert(CONFIG_SYS_BR1_PRELIM == LBC_BR_NAND); +static_assert(CONFIG_SYS_BR3_PRELIM == LBC_BR_CPLD); +static_assert(CONFIG_SYS_BR3_PRELIM == LBC_BR_CPLD); diff --git a/board/CZ.NIC/turris_1x/tlb.c b/board/CZ.NIC/turris_1x/tlb.c new file mode 100644 index 000000000000..e7113b0cd4c8 --- /dev/null +++ b/board/CZ.NIC/turris_1x/tlb.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <p...@kernel.org> + +#include <common.h> +#include <asm/mmu.h> +#include <linux/sizes.h> +#include <linux/build_bug.h> + +/* + * NOTE: e500v2 supports only following Book-E page sizes: + * + * TLB0: + * BOOKE_PAGESZ_4K + * + * TLB1: + * BOOKE_PAGESZ_4K + * BOOKE_PAGESZ_16K + * BOOKE_PAGESZ_64K + * BOOKE_PAGESZ_256K + * BOOKE_PAGESZ_1M + * BOOKE_PAGESZ_4M + * BOOKE_PAGESZ_16M + * BOOKE_PAGESZ_64M + * BOOKE_PAGESZ_256M + * BOOKE_PAGESZ_1G + * BOOKE_PAGESZ_4G + */ + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 */ + + /* ***** - Initial stack in L1 cache 16K */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * SZ_4K, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 1 * SZ_4K , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 1 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 2 * SZ_4K , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 2 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 3 * SZ_4K , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 3 * SZ_4K, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + + /* *I*** - Boot page 4K */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, + 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSR 1M */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, + CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - NOR 16M */ + /* This will be changed to *I*G* after relocation to RAM in board_early_init_r() */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - CPLD 256K (effective 128K) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, + CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G* - NAND 1M */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, + CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* *I*G* - PCIe MEM (bus 1 and 2) 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCIe MEM (bus 3) 4M (effective 2M) */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, + CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_4M, 1), + + /* *I*G* - PCIe I/O (all 3 buses) 256K (effective 192K) */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, + CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* ***G* - Initial SRAM in L2 cache 512K */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, + CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + SZ_256K, + CONFIG_SYS_INIT_L2_ADDR_PHYS + SZ_256K, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + /* **M** - SDRAM 2G */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 10, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + SZ_1G, + CONFIG_SYS_DDR_SDRAM_BASE + SZ_1G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 11, BOOKE_PAGESZ_1G, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); + +/* + * PCIe MEM TLB entry expects that second PCIe MEM window is mapped after the + * first PCIe MEM window. Check for this requirement. + */ +static_assert(CONFIG_SYS_PCIE2_MEM_VIRT == CONFIG_SYS_PCIE1_MEM_VIRT + SZ_512M); +static_assert(CONFIG_SYS_PCIE2_MEM_PHYS == CONFIG_SYS_PCIE1_MEM_PHYS + SZ_512M); + +/* + * PCIe I/O TLB entry expects that all 3 PCIe I/O windows are mapped one after + * another. Check for this requirement. + */ +static_assert(CONFIG_SYS_PCIE2_IO_VIRT == CONFIG_SYS_PCIE1_IO_VIRT + SZ_64K); +static_assert(CONFIG_SYS_PCIE2_IO_PHYS == CONFIG_SYS_PCIE1_IO_PHYS + SZ_64K); +static_assert(CONFIG_SYS_PCIE3_IO_VIRT == CONFIG_SYS_PCIE2_IO_VIRT + SZ_64K); +static_assert(CONFIG_SYS_PCIE3_IO_PHYS == CONFIG_SYS_PCIE2_IO_PHYS + SZ_64K); diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c new file mode 100644 index 000000000000..8f2400f79e05 --- /dev/null +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <p...@kernel.org> + +#include <common.h> +#include <init.h> +#include <env.h> + +#include "../turris_atsha_otp.h" + +/* + * Reset time cycle register provided by Turris CPLD firmware. + * Turris CPLD firmware is open source and available at: + * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v + */ +#define TURRIS_CPLD_RESET_TIME_CYCLE_REG ((void *)CONFIG_SYS_CPLD_BASE + 0x1f) +#define TURRIS_CPLD_RESET_TIME_CYCLE_300MS BIT(0) +#define TURRIS_CPLD_RESET_TIME_CYCLE_1S BIT(1) +#define TURRIS_CPLD_RESET_TIME_CYCLE_2S BIT(2) +#define TURRIS_CPLD_RESET_TIME_CYCLE_3S BIT(3) +#define TURRIS_CPLD_RESET_TIME_CYCLE_4S BIT(4) +#define TURRIS_CPLD_RESET_TIME_CYCLE_5S BIT(5) +#define TURRIS_CPLD_RESET_TIME_CYCLE_6S BIT(6) + +int misc_init_r(void) +{ + turris_atsha_otp_init_mac_addresses(0); + return 0; +} + +int show_board_info(void) +{ + u32 version_num, serial_num; + int err; + + err = turris_atsha_otp_get_serial_number(&version_num, &serial_num); + + /* + * Turris 1.0 boards have version_num 0x5. + * Turris 1.1 boards have version_num 0x6, 0x7, 0x8 and 0x9. + */ + printf("Model: Turris 1.%c\n", err ? 'x' : + (be32_to_cpu(version_num) >= 0x6) ? '1' : '0'); + + if (err) + printf("Serial Number: unknown\n"); + else + printf("Serial Number: %08X%08X\n", be32_to_cpu(version_num), + be32_to_cpu(serial_num)); + + err = checkboard(); + if (err) + return err; + + return 0; +} + +static void handle_reset_button(void) +{ + const char * const vars[1] = { "bootcmd_rescue", }; + + /* + * Ensure that bootcmd_rescue has always stock value, so that running + * run bootcmd_rescue + * always works correctly. + */ + env_set_default_vars(1, (char * const *)vars, 0); + + /* Check if red reset button was hold for at least six seconds. */ + if (in_8(TURRIS_CPLD_RESET_TIME_CYCLE_REG) & TURRIS_CPLD_RESET_TIME_CYCLE_6S) { + const char * const vars[2] = { + "bootcmd", + "distro_bootcmd", + }; + + /* + * Set the above envs to their default values, in case the user + * managed to break them. + */ + env_set_default_vars(2, (char * const *)vars, 0); + + /* Ensure bootcmd_rescue is used by distroboot */ + env_set("boot_targets", "rescue"); + + printf("RESET button was pressed, overwriting boot_targets!\n"); + } else { + /* + * In case the user somehow managed to save environment with + * boot_targets=rescue, reset boot_targets to default value. + * This could happen in subsequent commands if bootcmd_rescue + * failed. + */ + if (!strcmp(env_get("boot_targets"), "rescue")) { + const char * const vars[1] = { + "boot_targets", + }; + + env_set_default_vars(1, (char * const *)vars, 0); + } + } +} + +int last_stage_init(void) +{ + handle_reset_button(); + return 0; +} diff --git a/configs/turris_1x_nor_defconfig b/configs/turris_1x_nor_defconfig new file mode 100644 index 000000000000..ada6789dd6cd --- /dev/null +++ b/configs/turris_1x_nor_defconfig @@ -0,0 +1,50 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set +CONFIG_TARGET_TURRIS_1X=y +CONFIG_AHCI=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_MP=y +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTO_COMPLETE is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_EEPROM is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_NVME_PCI=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y diff --git a/configs/turris_1x_sdcard_defconfig b/configs/turris_1x_sdcard_defconfig new file mode 100644 index 000000000000..fcceb12cbcd1 --- /dev/null +++ b/configs/turris_1x_sdcard_defconfig @@ -0,0 +1,66 @@ +CONFIG_PPC=y +CONFIG_SPL=y +CONFIG_MPC85xx=y +CONFIG_TARGET_TURRIS_1X=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_MP=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="SDCARD" +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LZMADEC=y +CONFIG_CMD_UNLZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x52 +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_NVME_PCI=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_ESPI=y +CONFIG_USB=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_MAX6370=y +CONFIG_FAT_WRITE=y diff --git a/include/configs/turris_1x.h b/include/configs/turris_1x.h new file mode 100644 index 000000000000..576767a6cbec --- /dev/null +++ b/include/configs/turris_1x.h @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár <p...@kernel.org> + +#ifndef _CONFIG_TURRIS_1X_H +#define _CONFIG_TURRIS_1X_H + +#include <linux/sizes.h> + +/* + * Turris 1.x memory map: + * + * 0x0000_0000 - 0x7fff_ffff 2 GB DDR cacheable + * 0x8000_0000 - 0xbfff_ffff 1 GB PCIe MEM (bus 1-2) non-cacheable + * 0xc000_0000 - 0xc01f_ffff 2 MB PCIe MEM (bus 3) non-cacheable + * 0xc020_0000 - 0xeeff_ffff 750 MB unused + * 0xef00_0000 - 0xefff_ffff 16 MB NOR (CS0) non-cacheable + * 0xf000_0000 - 0xf8f7_ffff 143 MB unused + * 0xf8f8_0000 - 0xf8ff_ffff 512 kB L2 SRAM cacheable (early boot, SD card only) + * 0xf900_0000 - 0xff6f_ffff 103 MB unused + * 0xff70_0000 - 0xff7f_ffff 1 MB CCSR non-cacheable (SPL only) + * 0xff80_0000 - 0xff80_7fff 32 kB NAND (CS1) non-cacheable + * 0xffa0_0000 - 0xffa1_ffff 128 kB CPLD (CS3) non-cacheable + * 0xffc0_0000 - 0xffc2_ffff 192 kB PCIe IO non-cacheable + * 0xffd0_0000 - 0xffd0_3fff 16 kB L1 stack cacheable (early boot) + * 0xffe0_0000 - 0xffef_ffff 1 MB CCSR non-cacheable (not in SPL) + * 0xffff_f000 - 0xffff_ffff 4 kB Boot page non-cacheable + */ + +/* + * Global settings + */ + +/* + * CONFIG_ENABLE_36BIT_PHYS needs to be always defined when processor supports + * 36-bit addressing (which is case for P2020), also when only 32-bit addressing + * mode is used. Name of this config option is misleading and should have been + * called SUPPORT instead of ENABLE. + * When CONFIG_PHYS_64BIT is set then 36-bit addressing is used, when unset then + * 32-bit addressing is used. Name of this config option is misleading too and + * should have been called 36BIT and ENABLED, not 64BIT. + * Due to performance reasons (see document AN4064), Turris 1.x boards use only + * 32-bit addressing. Also all config options are currently defined only for + * 32-bit addressing, so compiling U-Boot for 36-bit addressing is not possible + * yet. + */ +#define CONFIG_ENABLE_36BIT_PHYS +#ifdef CONFIG_PHYS_64BIT +#error "36-bit addressing is not implemented for this board" +#endif + +#define CONFIG_HWCONFIG +#define CONFIG_L2_CACHE +#define CONFIG_SYS_L2_SIZE SZ_512K +#define CONFIG_BTB /* Enable Branch Prediction */ + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +#define CONFIG_SYS_MONITOR_LEN CONFIG_BOARD_SIZE_LIMIT + +/* + * Boot settings + */ + +#ifdef CONFIG_SDCARD + +/* + * Booting from SD card + * BootROM configures L2 cache as SRAM, loads image from SD card into L2 SRAM + * and starts executing directly _start entry point in L2 SRAM. Therefore reset + * vector is not used and maximal size of the image is L2 cache size. For builds + * with SPL there is no limit of U-Boot proper as BootROM loads SPL which then + * loads U-Boot proper directly into DDR. + */ + +#define CONFIG_SYS_MPC85XX_NO_RESETVEC + +/* For SD card builds without SPL it is needed to set CONFIG_SYS_RAMBOOT */ +#ifndef CONFIG_SPL +#define CONFIG_SYS_RAMBOOT +#endif + +#ifdef CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_PAD_TO 0 +#endif + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR +#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_L2_SIZE + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * SZ_512) +#else +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_L2_SIZE +#endif +#define CONFIG_SYS_MMC_U_BOOT_SIZE CONFIG_BOARD_SIZE_LIMIT +#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif + +#else + +/* + * Booting from NOR + * Last 4kB page of the NOR is mapped into CPU address space and CPU starts + * executing last instruction of that page, which is reset vector address. + * We have 16 MB large NOR memory, so define correct reset vector address. + */ + +#define CONFIG_RESET_VECTOR_ADDRESS (CONFIG_SYS_FLASH_BASE + SZ_16M - 4) + +#endif + +/* + * CONFIG_BOARD_SIZE_LIMIT must be hex number because it is used in Makefile. + * For NOR build, size of the U-Boot binary must always be 768 kB. + * For SD card build with SPL, there is no limit, just broken build system which + * cannot fill CONFIG_SYS_MMC_U_BOOT_SIZE and CONFIG_SYS_MONITOR_LEN values + * automatically. So choose it as lowest value as possible with which build + * process does not fail, to minimize final binary size. + * For SD card build without SPL, there is upper limit of L2 cache size. + */ +#ifndef CONFIG_SDCARD +#define CONFIG_BOARD_SIZE_LIMIT 0x000c0000 /* 768 kB */ +#elif defined(CONFIG_SPL) +#define CONFIG_BOARD_SIZE_LIMIT 0x00100000 /* 1 MB */ +#else +#define CONFIG_BOARD_SIZE_LIMIT 0x00080000 /* 512 kB - must be same as CONFIG_SYS_L2_SIZE */ +#endif + +/* + * Initial stack in L1 cache + */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CONFIG_SYS_INIT_RAM_SIZE SZ_16K +#define CONFIG_SYS_INIT_RAM_LOCK + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Initial SRAM in L2 cache + */ + +/* Initial SRAM is used only for SD card boot in first stage image */ +#ifdef CONFIG_SDCARD +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SPL_RELOC_TEXT_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * SZ_1K) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * SZ_1K) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * SZ_1K) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 * SZ_1K) +#endif +#endif + +/* + * CCSR + */ + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* + * U-Boot _start code expects that if CCSRBAR is configured to its default + * location and automatically relocate it to the new CONFIG_SYS_CCSRBAR_PHYS + * location. Relocation to the new location can be skipped by defining macro + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. + * + * All addresses in device tree are set to according the new relocated CCSRBAR. + * So device tree code cannot be used when CONFIG_SYS_CCSR_DO_NOT_RELOCATE is + * set. + * + * If CCSRBAR is is not configured to its default location then _start code + * hangs or crashes. + * + * So relocation of CCSRBAR must be disabled in every code which runs before + * U-Boot proper (e.g. SPL), otherwise U-Boot proper's _start code crashes. + */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + +/* + * DDR + */ + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define SPD_EEPROM_ADDRESS 0x52 + +/* + * NOR + */ + +#define CONFIG_SYS_FLASH_BASE 0xef000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16 MB */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_QUIET_TEST + +/* + * NAND + */ + +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#define CONFIG_NAND_ECC_BCH + +/* + * CPLD + */ + +#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +/* + * Serial Port + */ + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) + +#define CONFIG_SYS_BAUDRATE_TABLE { 600, 1200, 1800, 2400, 4800, 9600, \ + 19200, 38400, 57600, 115200, 230400, \ + 460800, 500000, 576000, 921600, \ + 1000000, 1500000, 2000000, 3000000 } + +/* + * PCIe + */ + +/* PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card */ +#define CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_VIRT + +/* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */ +#define CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_VIRT +#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_VIRT + +/* PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller */ +#define CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_VIRT +#define CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT + +#define CONFIG_PCI_SCAN_SHOW /* Show pci devices on startup */ + +/* + * Ethernet + */ + +#define CONFIG_ETHPRIME "ethernet@26000" /* Primary ethernet device */ + +/* + * USB + */ + +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +/* + * eSDHC + */ + +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define SDHC_WP_IS_GPIO /* SDHC_WP pin is not connected to SD card slot, it is GPIO pin */ + +/* + * ATA/SCSI + */ + +#define CONFIG_LBA48 /* Enable support for 137+ GB disks */ +#define CONFIG_SYS_64BIT_LBA /* Enable support for 2.1+ TB disks */ + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* Allow baudrate change argument for loads */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ SZ_64M /* Initial Memory for Linux */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* + * Environment Configuration + */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(NVME, nvme, 0) \ + func(SCSI, scsi, 0) \ + func(USB, usb, 0) \ + func(USB, usb, 1) \ + func(USB, usb, 2) \ + func(USB, usb, 3) \ + func(USB, usb, 4) \ + func(UBIFS, ubifs, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +/* These boot source switches macros must be constant numbers as they are stringified */ +#define __SW_BOOT_MASK 0x03 +#define __SW_BOOT_NOR 0xc8 +#define __SW_BOOT_SPI 0x28 +#define __SW_BOOT_SD 0x68 +#define __SW_BOOT_SD2 0x18 +#define __SW_BOOT_NAND 0xe8 +#define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ + +#include "p1_p2_bootsrc.h" + +#define REBOOT_ENV_SETTINGS \ + RST_NOR_UP_CMD(reboot_to_nor, echo Rebooting to NOR bootloader;) \ + RST_SD_CMD(reboot_to_sd, echo Rebooting to SD bootloader;) \ + RST_DEF_CMD(reboot_to_def, echo Rebooting to default bootloader;) \ + "" + +#define BOOTCMD_RESCUE \ + "setenv bootargs root=mtd2 rw rootfstype=jffs2 console=ttyS0,115200; " \ + "bootm 0xef020000 - 0xef000000" \ + "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2100000\0" \ + "scriptaddr=0x3000000\0" \ + "pxefile_addr_r=0x3100000\0" \ + "ramdisk_addr_r=0x4000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdt_addr=0xef000000\0" \ + "bootubipart=rootfs\0" \ + "bootubivol=rootfs\0" \ + "bootcmd_rescue=" BOOTCMD_RESCUE "\0" \ + REBOOT_ENV_SETTINGS \ + BOOTENV + +#endif /* _CONFIG_TURRIS_1X_H */ -- 2.20.1
