[PATCH] arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration

[Michal Simek]

From: Neal Frager <neal.fra...@amd.com>

This patch fixes the DP audio and video PLL configurations for the 
zynqmp-sm-k26-revA som.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)
  - DP system time clock PLL should use RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Register 0xFD1A007C configures the DP system time clock PLL.

Signed-off-by: Neal Frager <neal.fra...@amd.com>
Signed-off-by: Michal Simek <michal.si...@amd.com>
---

 board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c 
b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
index ed025790bc3a..e5598807e8c1 100644
--- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
@@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void)
        psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U);
        psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
        psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+       psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+       psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
+       psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
        psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
        psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
        psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
-- 
2.36.0