On Thu, 26 May 2022 at 07:38, Paweł Anikiel <p...@semihalf.com> wrote: > > Before relocating to SDRAM, the ECC is initialized by clearing the > whole SDRAM. In order to speed this up, dcache_enable is used (see > sdram_init_ecc_bits). > > Since commit 503eea451903 ("arm: cp15: update DACR value to activate > access control"), this no longer works, because running code in OCRAM > with the XN bit set causes a page fault. Override dram_bank_mmu_setup > to disable XN in the OCRAM and setup DRAM dcache before relocation. > > Signed-off-by: Paweł Anikiel <p...@semihalf.com> > --- > arch/arm/mach-socfpga/misc_arria10.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) >
Reviewed-by: Simon Glass <s...@chromium.org>