On Dec 8, 2010, at 8:55 PM, York Sun wrote: > Added fsl_ddr_get_version() function to poll DDRC IP version (major, minor, > errata) to determine if unique mode registers are available. This function may > be needed for future other platforms if such a feature exists. If true, always > use unique mode registers. Dynamic ODT is enabled if needed. The table is > documented in doc/README.fsl-ddr. > > Enable address parity and RCW by default for RDIMMs. > > Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for > quad-rank RDIMMs. > > Use a formula to calculate rodt_on for timing_cfg_5. > > Signed-off-by: York Sun <york...@freescale.com> > --- > arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 18 ++ > arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 305 +++++++++++++++++++++++++---- > arch/powerpc/cpu/mpc8xxx/ddr/options.c | 308 +++++++++++++++++++++++++++++- > arch/powerpc/include/asm/fsl_ddr_sdram.h | 18 ++ > board/freescale/corenet_ds/ddr.c | 125 ++++++-------
do we really need to mix corenet_ds/ddr.c in this patch? > doc/README.fsl-ddr | 67 +++++++- > 6 files changed, 723 insertions(+), 118 deletions(-) What about other DDR3 boards like P2020DS? Are they impacted by this patch? - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
